Re: SRAM hspice netlist
I used this netlist for simulate the cell (0.35u) in three modes (write-hold-read) in a transient:
SRAM cell 6T
.include modn.mod
.include modp.mod
*sources
**supply
vdd 1 0 dc 0.4
**access control
vwl wl 0 pulse(0 0.4 2m 100u 100u 2m 8m)
**data
vbl BL1 0 dc 0.4
vblr BLR1 0 pulse(0 0.4 5m 100u 100u 15m 1)
**control
vr_w r_w 0 pulse(0 0.4 0 1u 1u 10m 1)
*devices
**switches
GBL BL1 BL VCR PWL(1) r_w,0 0,1e20 1m,1e-20
GBLR BLR1 BLR VCR PWL(1) r_w,0 0,1e20 1m,1e-20
**mos transistors - latch
m1 Q QR 0 0 modn w=1u l=0.35u
m2 Q QR 1 1 modp w=1u l=0.35u
m3 QR Q 0 0 modn w=1u l=0.35u
m4 QR Q 1 1 modp w=1u l=0.35u
**mos transistors - data access
m5 BL wl Q 0 modn w=10u l=0.35u
m6 BLR wl QR modn w=10u l=0.35u
*analysis
.tran 1u 15m 0
.option post
.end
you could change the mos tansistors models