SRAM density and energy efficiency

You can simulate power for a given design*process
(density) - presuming you had the models, which you
don't and almost certainly can't.

Going the other way, from a power result to a
density, would be pretty impractical if you mean to
address the question across foundry generations
etc. See "can't"**N for probability of success.

And RAM design often involves "strategic cheating"
of groundrules, and sub-"minimum" devices which
are more bothered by narrow- and short-channel
effects.

A lot of RAM performance and dynamic power relates
to interconnect loading, read / write cycle design
(like how long per read cycle the precharge and
sense amp circuitry is energized). Static power wants
to know about leakage (generally poorly modeled)
and VT and IDsat (of those nonstandard device
geometries, for which it's unlikely you'd be able to
even get WAT data let alone a righteous statistical
model, presuming you care to go that deep into
simulation fantasy land).

shockingshockley said:

Hello. Is it possible to simulate SRAM density versus the energy or power consumption? If yes, what factors or parameters do I need to consider for SRAM density? transistor length vs energy? Thanks in advance.

Click to expand...

for some really simple first order estimations, there are memory models available. for anything more complicated, you need foundry data to make estimations/extrapolations.