SRAM CONTROLLER

[xIce]

Hello everybody,

Firstly, I do not know if this is the right section to post this thread but I hope someone can help me understand a thing.

So basically the image represents a SRAM Controller that I need to realise. The AHB Lite Interface only consists of the two Slaves according to the task: one has a Clk_slow which is 100 Mhz and the other a 150 Mhz Clk_med. That is why there is the block Synchronization which I was thinking to realise by implementing a Mux Synchronizer or an Handshaking Synchronizer.

My problem is with the Port Arbitration that I've never met in my life. I mean, my reasoning lets me think that is something used to control when more requests from the two Slaves are send to the SRAM (write/read requests) but I really don't know how I could realise it, like which circuit I should use, its micro architecture and stuff like this.

Really hope someone can help me.

Kind regards,

 

[dpaul]

Do you have access to an AHB to AHB synchronous bridge?

Documentation – Arm Developer

developer.arm.com

It might help you.

I have never used it myself so cannot give you descriptions.

​

 

[xIce]

I do not have acccess to a bridge, it is just a block that should handle the request coming from the AHB Lite Slaves and handle the priority I guess. I should understand its signals and how to build it with combinational logic