sram architecture and its peripherals

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oly

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I want to create a complete 6T sram architecture with all its peripherals (row decoder,column decoder,sense amplifier etc.). using hspice . i want to know the schematic of 6T sram with its peripherals.
 

Already the 2nd G00GLE place of finding shows a research paper "Performance Evaluation of 6T Sram Cell Structure and Peripheral Circuitry" which contains an overview and evaluation of several different pre-decoders and row and column address decoders.

Moreover you could search at G00GLE books.

You should tell what you exactly want!
 

sir i want to know how the decoder circuitry and sense amplifier (different parts) are connceted with a 6T sram cell.
i want internal structure of every parts rather than block diagram.
 

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