Spyglass error with logical operation on a vector

[rahdirs]

Hi everyone,

After running Spyglass, I'm seeing a couple of errors being reported on logical OR operation.
Posting an example here:

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Code Verilog - [expand]
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wire [5:0] a;
wire           b, c, d;
 
assign d = c & (a || b);

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I had this code initially, so the initial error was that the operator || has a width mismatch on the operands. This was puzzling to me as Verilog usually is able to type-cast signal b automatically to 6 bit vector & the resulting output of the logical operation should be a 1 bit variable. Anyway, i did a manual casting & changed it to :

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Code Verilog - [expand]
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assign d = c & (a || ({5'b0,b}));

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After manually extending b, i see a new error that logical operation (in this case ||) is not allowed on a vector. Does anyone know why Lint is reporting an error on logical operations on a vector ?
I can think of the below solution to this but it makes the code so messy.

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Code Verilog - [expand]
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assign d = c & (~(!(a | ({5'b0,b}))));

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Looking forward to your suggestions !!

 

[vGoodtimes]

so d(0) = c[0] bitwise-and (a[5:0] logical-or b[0])

do you want: assign d = c && ((a!=0) || b); ?

 

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or you can write it as: assign d = c && (|a || b); // perform a reduction OR on "a" this is equivalent to a!=0

Logical operations on vectors with scalars is allowed as the vector is interpreted with either ==0 or !=0, but this is ambiguous. It is preferred IMO to use reduction operations first on any vector to convert it to a scalar (which is what the comparison operator does). There are also subtle gotchas with using logical operators on vectors given that the bitwise operators will behave differently in some situations.

Technically I would not write the d assignment as above, instead I would write this as:
assign d = (c && (|a || b) ? 1'b1 : 1'b0;
or by assigning the equivalent logic operations:
assign d = c & (|a | b); // the reduction OR is useful for both logical or bitwise operators

Of all of these I prefer the third assignment as everything is just bits and logic gates.

Furthermore would avoid writing assignments with a mix of logical and bitwise operators in the same statement like you did in your first post as it requires more effort from anyone looking at the code to determine if it is correct (besides throwing lint warnings due to ambiguous code).

 

[vGoodtimes]

idk, the last one is weird. it uses bitwise operations on 1b values. So an astute reader will question why a possibly multi-bit operator is being used. Did the writer think the operator was on multiple bits? why would the writer use a confusable operator?

 

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idk, the last one is weird. it uses bitwise operations on 1b values. So an astute reader will question why a possibly multi-bit operator is being used. Did the writer think the operator was on multiple bits? why would the writer use a confusable operator?

was this referring to my last one done on single bits? assign d = c & (|a | b);

Using bitwise operators operates on each bit in each position of the vector, e.g. it acts like an AND gate on every single bit with the exact same bit of the other vector. Using it on a 1b value works in an identical fashion to a multi-bit value as a 1b is the same as a [0:0] vector. I don't see where this is an issue. So what is the 1b operator that implements an AND, OR, XOR, NOT, etc gates if not the bitwise operator? Logical operators are not the same as the bitwise operators and won't behave like gates in all instances (even though people regularly use them as if they do).

The fact that Verilog is loosely typed unlike VHDL (which has a boolean type) may be confusion things. Logical operators should only be used where VHDL boolean types are used, but can still be used anywhere in Verilog code (even if incorrect). In cases of vectors and scalar bits the logical operators can give incorrect results. Unfortunately I no longer have a link to a blog page (I would point people to) that explained the difference between using Logical and Bitwise operators.