viju
Member level 4
Hi ,
I have a design which has many FIFOs in it. I'm running SPY Glass CDC analysis on it. What I found it report is that Spy Glass is not able to detect the FIFO architecture and generates lots of Error / Warnings like "Data hold check:FAILED" Ac_cdc01a. for the wr and rd pointer flops. It also shouts for underflow/ overflow. But my design uses Full/empty signal and based on it it write/read from FIFO. So why SPyGlass is compaining about it?
I tried -enable_fifo switch to get rid of these warnings. But no help with this. Can any one help me here ?
Another question is , in my design some registers will get a value during initial time of booting only after that it is going be static and hence I have used 2 flop sync but spyglass shouts warning that only 2 flop sync used and data hold check fail. How to tell spyglass not to shout for such signals?
Thanks,
VJ
I have a design which has many FIFOs in it. I'm running SPY Glass CDC analysis on it. What I found it report is that Spy Glass is not able to detect the FIFO architecture and generates lots of Error / Warnings like "Data hold check:FAILED" Ac_cdc01a. for the wr and rd pointer flops. It also shouts for underflow/ overflow. But my design uses Full/empty signal and based on it it write/read from FIFO. So why SPyGlass is compaining about it?
I tried -enable_fifo switch to get rid of these warnings. But no help with this. Can any one help me here ?
Another question is , in my design some registers will get a value during initial time of booting only after that it is going be static and hence I have used 2 flop sync but spyglass shouts warning that only 2 flop sync used and data hold check fail. How to tell spyglass not to shout for such signals?
Thanks,
VJ