Spur Problem in a PLL Circuit [pls hlp me]

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Re: PLL Problem [pls hlp me]

Hello Fred
About the PLL:

- PLL frequency is about 3.5GHz
- I'm using ADF4156 of Analog Devices (fractional)
- I'm using AD820 as Op-Amp of loop filter
- Supply voltages used for op-amp are +24V and GND
- My reference frequency is about 3.2MHz (after dividing by R)
- The output frequency of PLL is as I expect, so it seems that PLL locks; but digital lock detect output is low!!
- I'm using +5V for Vp of ADF4156

WHAT SHOULD I DO?
 

Re: PLL Problem [pls hlp me]

I notice from the AD820 data sheet that that op amp is very sensitive to capacitive loading. Read the spec sheet section on Output Characteristics. It is VERY possible that your circuit's big C3 capacitor is making the op amp oscillate all on its own. Did you try removing C3 yet?
 

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    elec350

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Re: PLL Problem [pls hlp me]

Rich wrote:


I removed C3, but ±n50kHz spurs are present!

another solution please!
 

Re: PLL Problem [pls hlp me]


So just getting the rest of the information from that first design:
1. What is the output frequency, what is the phase detector frequency?
2. I assume it is fractional-N, what is the modulus?
3. is it locked - i.e. is the output frequency correct - have you measured it on a counter and compared it to the ref frequency measured with a counter?
4. Vp supply to the chip is 5V, op amp has +24V
5. what is the voltage on the + input to the op amp and the VCO voltage when locked?

When the spurs changed from 50kHz spacing, what changes did you make to the chip programming?
 

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    elec350

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Re: PLL Problem [pls hlp me]

Hello friends
A disappointing thing: my PLL doesn't lock! It seems that it isn't locking. What should I do now?
 

Re: PLL Problem [pls hlp me]

elec350 said:
Hello friends
A disappointing thing: my PLL doesn't lock! It seems that it isn't locking. What should I do now?
Click to expand...

Go back to basics:
0. check power supplies etc..
1. double check the chip programming, if possible use the test output and send the outputs of the R and N counters there and check the frequency.
2. break the loop before the VCO, use a power supply to drive the VCO, start from the bottom of the band and sweep slowly to the top. While you do this monitor the output of the loop filter on an oscilloscope and the VCO frequency on a spectrum analyzer or counter. When the VCO frequency is too low the loop filter output should be saturated high trying to increase the frequency. As you pass over the 'programmed' frequency the loop filter output should switch to being saturated low as it is now trying to reduce it.
3. if no switching was observed in (2), or at the wrong frequency, then the chip is programmed incorrectly
4. if the loop filter output switched low to high instead of high to low the the charge pump polarity is reversed
5. from (2) measure the VCO voltage required to get the right frequency and verify that this is within the output range of the op amp. Calculate what the op amp input voltage will be for this and check that this is within the op amp common mode range
6. double check the loop filter components and verify their values with the ADIsimPLL design
7. if you have doubts whether the charge pump is set up correctly you can terminate it into 100 ohms by connecting 200 ohm resistors to Vp and to gnd, then as you alter the VCO voltage as in (2) you will see voltage pulses on it and from their amplitude you can work out the charge pump current. You need to disconnect the loop filter from the charge pump to do this test.
 

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    elec350

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Re: PLL Problem [pls hlp me]

Hello Fred
thanks for your descriptions. But before doing your tests, I should another point: the output isn't locking, but sometimes it jumps to desired frequency, then jumps to other frequencies. It seems that the PLL isn't stable. In ADIsimPLL, I chose phase margin for 60° and loop filter bandwidth of 300kHz. May it be wrong?
 

Re: PLL Problem [pls hlp me]


What is your phase detector frequency? What is the modulus?
 

Re: PLL Problem [pls hlp me]

Hello Fred
Mod = 130 and PD frequency is 3.2MHz
 

Re: PLL Problem [pls hlp me]

So your vco frequency is 130 * 3.2 MHz = 416 MHz?

What country are you in? You do not seem to be understanding the questions.
 

Re: PLL Problem [pls hlp me]

Excuse me Rich
I think that you wrote a wrong relationship. The true relation is:

fout = 3.2MHz × ( INT + frac/MOD)
 

Re: PLL Problem [pls hlp me]

elec350 said:
Hello Fred
Mod = 130 and PD frequency is 3.2MHz
Click to expand...

OK then with a 3.2MHz PD freq you should be able to have a 300kHz LBW.

Have you looked at the CP output to see if things are occurring at something like a 3.2MHz rate?

You would expect to see fractional spurs at multiples of 12.3kHz, however depending on register settings these could be at multiples of 24.6kHz or 49.2kHz and so on.

Have you set the PHASE value to 1 and enabled the SD bit - this gives most repeatable spur performance and is good for testing.
 

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    elec350

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Re: PLL Problem [pls hlp me]

Hello Fred
You wrote:

Have you set the PHASE value to 1 and enabled the SD bit - this gives most repeatable spur performance and is good for testing.
Click to expand...

I did this test, but the output didn't changed.
May the problem comes from tuning voltage line?
 

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