spur and phase noise , which is matter ?

[xihuwang]

spur and phase noise ?

Hi:
Dose anyone know wheather phase noise is included in the phase noise
simulation result in spectre ? I saw a peak at the freqeucy of (fo - fm) .
The second question is wheather should I include the reference spur
when calculate or simulate the peak long and short term jitter peak ?
My last question is how to calculate or simulate using specte the jitter
or phase noise if spur must be considered .

I saw many papers and IP core of pll frequency synthesizer give
long term and short term jitter or phase noise. But I think it is not
right because I think phase noise is the result of device randon noise.

And I think for frequency synthesizer it is the frequency jitter ,but not
the phase jitter dose matter.

I am totally confused with spur , phase noise , jitter ( cycle-to cycle, period-to-period
...jitter ) when design a pll frequency synthesizer.

I get the eye diagram in spectre, and I find the jitter is small for good charge pump
but large jitter for bad charge pump . How to explain it . Does it has meaning to
see the eye diagram for frequency synthesizer I I think the phase jitter does
not matter for frequency synthesizer which just need to output period stability
clock signal)

Thanks forward and need your help !

Best Regards!

 

[saro_k_82]

Re: spur and phase noise ?

Hi:
Dose anyone know wheather phase noise is included in the phase noise
simulation result in spectre ?

Not sure what this means

I saw a peak at the freqeucy of (fo - fm) .

Can you provide more details, what is fo, fm, whether you are simulating the closed loop PLL or just the VCO, etc

The second question is wheather should I include the reference spur
when calculate or simulate the peak long and short term jitter peak ?

You have to

My last question is how to calculate or simulate using specte the jitter
or phase noise if spur must be considered .

Jitter and phase noise display the same phenomenon in different domains. So if you cannot get rid of the spur, it is going to affect the jitter numbers. Suppressing the spur in calculations is not the right way to obtain jitter.

I saw many papers and IP core of pll frequency synthesizer give
long term and short term jitter or phase noise. But I think it is not
right because I think phase noise is the result of device randon noise.

Why do you think so? Phase noise is a result of device random noise, mismatches in the all the components, substrate noise, supply noise, load, etc of which the device noise is the one you dont have too much control and is generally the major part.

And I think for frequency synthesizer it is the frequency jitter ,but not
the phase jitter dose matter.

Jitter by definition is the time domain uncertainty about the zero crossing (or CM level crossing). There is no term in use called frequency jitter. Phase jitter is same as jitter AFAIK.

I am totally confused with spur , phase noise , jitter ( cycle-to cycle, period-to-period
...jitter ) when design a pll frequency synthesizer.

You need to refer to a good book. I'm afraid you cant get anyone to help you gain complete understanding of a PLL here.

I get the eye diagram in spectre, and I find the jitter is small for good charge pump
but large jitter for bad charge pump . How to explain it . Does it has meaning to
see the eye diagram for frequency synthesizer I I think the phase jitter does
not matter for frequency synthesizer which just need to output period stability
clock signal)

In that case you have to simulate the PFD-CP for phase noise and verify that it is the major source. Phase noise definitely matters to a frequency synthesizer more than the eye diagram.