[SOLVED] sprintf like function in VHDL

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syedshan

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sprintf like function in VHDL...or should I say writing to STRING inVHDL

Dear all,

I need to take input mutliple files in VHDL for simulation. Files are names similar, just their indexing is differnet.
Is there any function like in C ++ we use to have
sprintf(str , "name%d.txt ",i);
Click to expand...

I looked over internet and could not find. What I think is there is no such thing, but I need it.
Later I intend to use this string in the FILE Name location


Bests,
 

Hi,
Thank you for reply.
Yes for single file I can read but I need to read multiple files, around 100 or more, and that turn after turn.
 

just concatenate the name:

s := "name" & integer'image(i) & ".txt";

- - - Updated - - -

PS. I think I know what the next problem will be - length of the string s
 

Open them one by one using a loop function with indexed file names
 

AdvaRes said:
Open them one by one using a loop function with indexed file names
Click to expand...

If I understand syedshan correctly, the loop isn't the problem, it's generating the filenames that is the problem. That's why he's looking for the sprintf equivalent in VHDL.

In verilog you can just use $sformat, but that's no use if it must be done in VHDL. In which case I think TrickyDicky's suggestion is best. Use concatenation, and make sure that you declare s to be large enough to hold the largest possible string you're going to use.
 

Thank you TrickyDicky

PS. I think I know what the next problem will be - length of the string s
Click to expand...

This is one case, but I think this can be resolved using the if-else statement.
But the thing is when I used
Code: 
 file   infile    : text is in str;   --declare input file

--where variable str: STRING(1 to 9) := "data0.txt";

then the simulation does not proceed and although now I have closed that simulation it somewhat did not accepted to open the file with this thing. when I changed back directly giving filename it worked again.
instead of variable I also tried signal as well

Code: 
Open them one by one using a loop function with indexed file names

This is the problem I am facing in VHDL, it did not simply worked like in C++
 

First of all, as I said in the previous post, stop using the old version for file.

file infile : text is in str;

is VHDL '87 format. You should avoid this because you are forced to open the file when you declare it, and you cannot open a file in append mode (you can only overwrite the contents) You should use the '93 format:

file infile : text open read_mode is "some_file.txt";

Right, now thats out of the way, you can just declare a file like this:

file infile : text;

and then open it elsewhere with the FILE_OPEN procedure.

Code: 
process
  file infile : text;

  variable str : string(1 to 9);
begin
  ....
  for i in 0 to 9 loop
    str := "text" & integer'image(i)  & ".txt";

    FILE_OPEN(infile, str, read_mode);

    --do some stuff with the file

    FILE_CLOSE(infile);
  end loop;

  wait;
end process;
 
Use concatenation, and make sure that you declare s to be large enough to hold the largest possible string you're going to use.
Click to expand...

IN VHDL length of string should be equal to the string itself, no larger as used to be in C
 

Didn't know that one. It has to be exactly the same length? As in larger is not allowed and smaller is not allowed?

If you did concatenation in verilog and dumped your concatenated string in a big array of registers it doesn't have to be the exact same size. As long as it's small enough to fit. I suppose the "has to be the exact same size" constraint makes some sense in VHDL, since VHDL is fairly strict. Learn something new every day.
 

Yes, has to be the same length - as you suspect, its to do with strict typing.

When you declare a string:

signal str : string(1 to 9);

You're actually declaring a subtype of the string array of length 9 (plus for strings, it must always start at 1 and have a to direction)
So if you tried to do this:

str <= "Hello"

The second string is length 5, and hence the subtype length missmatches. Also, strings in VHDL are not null terminated like in C. But a string will have default values of (others => NUL).
 
Dear Tricky Dicky,

I am having unexpected error while trying to open with the string variable's name rather string itself.
Please see the simplest code first then the error.
Note that this same program when run with the name "data0.txt" itself runs perfectly fine, when I change to either variable or string post the below error

Finished circuit initialization process.
ERROR: In process top.vhd:reading
ENDFILE called on a file object that is not open
INFO: Simulator is stopped.
Click to expand...

Following is relevant code snippet
Code: 
architecture Behavioral of filehandle is
signal endoffile : bit := '0';
signal clock : std_logic := '0';
signal rst : std_logic := '1';
signal dataread : integer;
signal linenumber : integer:=1; --line number of the file read or written.
signal rd_en : std_logic := '0';
signal wr_en: std_logic := '1';
signal toggle : std_logic := '0';
signal empty : std_logic ;
--signal str : string(1 to 9) := "data0.txt";

begin

clock <= not (clock) after 5 ns;    --clock with time period 2 ns

process

begin
wait for 30 ns;		rst <= '0';
wait for 500 ns ;	
wait until endoffile = '1';
rd_en <= '1';
end process;

reading :
process(clock, rst)   
	variable str: STRING(1 to 9) := "data0.txt";	
--	file   infile    : text open read_mode is "data0.txt";   --declare input file	
    file infile : text open read_mode is str;
    variable  inline    : line; --line number declaration
    variable  dataread1    : integer;
begin

if(rst = '1') then
	endoffile <= '0';
	wr_en <= '0';
elsif(rising_edge(clock)) then
if (not endfile(infile)) then 
readline(infile, inline);       
read(inline, dataread1);
	wr_en <= '1';
	dataread <= dataread1;   
else
	endoffile <='1';  
	-- file_close(infile);	
	wr_en <= '0';
	rd_en <= '1';
end if;

if(rd_en = '1') then endoffile <= '0'; end if;
end if;

end process reading;
..
 

Is this the whole process? Are you sure you dont close the file? I see you have a file_close() procedure commented out , but there is no file_open procedure. What is the point of using a string variable if you're not going to use it?
 

why! I have used the string variable. please look at
Code: 
 file infile : text open read_mode is str;

Also as a next step as I told earlier I intend to use all the x number of files with different coefficients i.e. data0.txt, data1.txt, data2.txt
yes this is the whole process and yes I should have uncommented the file_close when I will be using the multiple files, since it is better to open 1 file at a time.

But why does it show the error I discussed earlier. I tried this many times, changing things as well.
 

I have no idea - opening a file with a variable like you did works fine for me (in modelsim 10.1) - and I cannot see a problem in your code.
 
syedshan said:
IN VHDL length of string should be equal to the string itself, no larger as used to be in C
Click to expand...

Note that you can avoid all of this sizing of the string stuff by constructing the filename string right in the file_open like this...

FILE_OPEN("text" & integer'image(i) & ".txt", str, read_mode);

Kevin Jennings
 
K-J said:
Note that you can avoid all of this sizing of the string stuff by constructing the filename string right in the file_open like this...

FILE_OPEN("text" & integer'image(i) & ".txt", str, read_mode);
Click to expand...

Neat, I like it. Why bother with declaring a buffer if you can use a builtin function that does that for you on the fly, and properly sized to boot.
 

TrickyDicky said:
I have no idea - opening a file with a variable like you did works fine for me (in modelsim 10.1) - and I cannot see a problem in your code.
Click to expand...

TrickyDicky,
Thank you very much for your all assistance...
As you mentioned that you run in modelsim I got idea that since I was running in ISIM, it had problem.
Hence what I conclude is that the problem I am having as discussed in reply #13, is actually when using ISIM as simulator.
Using Modelsim (6.5) it did work fine...

Thanks again,
 

I suggest trying to get a new version of modelsim - 6.5 is quite old (and has bugs that I got fixed!)
 

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