buenos
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hi.
if i use the spread spectrum clocking as the source clock of the system (single board computer, with AMD Geode-LX processor), then what will happen with the memory timing?
the memory is a DDR-400 dimm memory module. the memory PLL in the processor derives the memory clock from the system clock input.
These DDR memory inerconnections are very sensitive for any jitter, scew, or unbalance in the reference clock. these degrade the timing budget, and if i rech the zero timing margins (setup and hold margins) then the memory interconnection will simply not work.
so, will this spread sp. clocking make the situation worse? will it degrade the timing budget?
if yes, then i can not use this sp.s.c. for my system.
if i use the spread spectrum clocking as the source clock of the system (single board computer, with AMD Geode-LX processor), then what will happen with the memory timing?
the memory is a DDR-400 dimm memory module. the memory PLL in the processor derives the memory clock from the system clock input.
These DDR memory inerconnections are very sensitive for any jitter, scew, or unbalance in the reference clock. these degrade the timing budget, and if i rech the zero timing margins (setup and hold margins) then the memory interconnection will simply not work.
so, will this spread sp. clocking make the situation worse? will it degrade the timing budget?
if yes, then i can not use this sp.s.c. for my system.
