Splitting the bits of a parameter for memory initialization in Verilog

I have written a SPI master in Verilog to write values to a PLL synthesizer chip. It works. I am now trying to clean up my code so that I can put all of the parameters for the PLL at the top of the file either as parameters or macro-style definitions. In a few cases, I have some values that are larger and need to be split in half to fit into the SPI words which are inferred ROM. Here is an abbreviated form of my code.


This code doesn't seem to work, and I wouldn't really want to implement it with a wire. How should I approach this problem? Thanks!

I'm not 100% sure if this is what you're asking, but maybe this:



Also keep in mind that parameters only 32-bits.

mrflibble said:

I'm not 100% sure if this is what you're asking, but maybe this:

---

Code Verilog - [expand]
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initial begin
    spi_reg[0] = MY_PARAMETER & 8'hFF;
    spi_reg[1] = (MY_PARAMETER >> 8) & 8'hFF;
// ...
end

---

Also keep in mind that parameters only 32-bits.

Click to expand...

Thank you. This answers my question. It crossed my mind to do it this way, but I was not sure whether it would be the cleanest method.

parasonic said:

Thank you. This answers my question. It crossed my mind to do it this way, but I was not sure whether it would be the cleanest method.

Click to expand...

Well, not sure if it is the cleanest way, but it is reasonably clean. As far as I'm concerned, wires and `defines are out for this purpose. This is readible enough. A bit depending on how many you have, and how maintainable it will become you could also define all the parameters elsewhere. As in you have your parameters with The Numbers [tm], and then you have other parameters, that are simply a repack of those numbers into the 8-bit parameters. Like I said, it depends a bit on how many, and the packing in question. If it 90% of it is like this, just a byte selected from a larger parameter ... then I'd stick with the example. If you get hundreds of bytes, with all sorts of convoluted packing then I'd put that in a separate file with some comments on the format.

You could do this concatenation in a single statement:


And even more easy in SystemVerilog with the streaming operator

dave_59 said:

And even more easy in SystemVerilog

Code:

spi_reg = {<<8{pll_r_counter}};

Click to expand...

Neat! Didn't know that one yet.