branek
Junior Member level 3
proteus spice models
Hello to everyone,
I designed spice model of LMV339 in proteus. It's working when I define next lines in model properties:
--
{PRIMITIVE=ANALOG,SUBCKT}
{SPICEFILE=LMV339.SML}
{SPICEMODEL=LMV339}
{SPICEPINS=+IP,-IP,VCC,GND,OP}
--
The problem is when I try to design full device (quad volt. comparator)
I deleted last line from above and added:
--
{PINOUT=LMV339}
--
where LMV339 pinout script is:
--
*PINOUT LMV339
ELEMENTS=4
PINS=14
IP +IP = 5,7,9,11
IP -IP = 4,6,8,10
OP OP = 2,1,14,13
PP VCC = 3,*,*,*
PP GND = 12,*,*,*
GATESWAP=TRUE
COMMON=VCC,GND
--
And when I put a two comparators(U1:A, U1:B) on schematic I'm geting next error report:
SIMULATION LOG
==============
Design: UNTITLED.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author: <NONE>
Created: 23/11/03
Modified: 24/11/03
Compiling source files...
Build completed OK.
Compiling netlist...
Linking netlist...
Partition analysis...
Simulating partition 1 [41045FF4]...
PROSPICE Release 6.2 SP0 (C) Labcenter Electronics 1993-2002.
SPICE Kernel Version 3f5. (C) Berkeley University ERL.
Reading netlist...
Reading SPICE models...
Linked SPICE file 'LMV339.SML'
Translated: H1 22 4 POLY(1) V1 0 748.395 -5483.95
to BH1 22 4 V=0+748.395*I(V1)+-5483.95*I(V1)*I(V1)
Translated: H2 4 21 POLY(1) V2 0 1211.03 -10110.3
to BH2 4 21 V=0+1211.03*I(V2)+-10110.3*I(V2)*I(V2)
Too few parameters for subcircuit type "LMV339" (instance: xU1:B)
FATAL: Failed to expand subcircuits.
Simulation FAILED due to fatal simulator errors.
What I'm doing wrong! I analyze other models, and they a built on the same way, I think!
Hello to everyone,
I designed spice model of LMV339 in proteus. It's working when I define next lines in model properties:
--
{PRIMITIVE=ANALOG,SUBCKT}
{SPICEFILE=LMV339.SML}
{SPICEMODEL=LMV339}
{SPICEPINS=+IP,-IP,VCC,GND,OP}
--
The problem is when I try to design full device (quad volt. comparator)
I deleted last line from above and added:
--
{PINOUT=LMV339}
--
where LMV339 pinout script is:
--
*PINOUT LMV339
ELEMENTS=4
PINS=14
IP +IP = 5,7,9,11
IP -IP = 4,6,8,10
OP OP = 2,1,14,13
PP VCC = 3,*,*,*
PP GND = 12,*,*,*
GATESWAP=TRUE
COMMON=VCC,GND
--
And when I put a two comparators(U1:A, U1:B) on schematic I'm geting next error report:
SIMULATION LOG
==============
Design: UNTITLED.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author: <NONE>
Created: 23/11/03
Modified: 24/11/03
Compiling source files...
Build completed OK.
Compiling netlist...
Linking netlist...
Partition analysis...
Simulating partition 1 [41045FF4]...
PROSPICE Release 6.2 SP0 (C) Labcenter Electronics 1993-2002.
SPICE Kernel Version 3f5. (C) Berkeley University ERL.
Reading netlist...
Reading SPICE models...
Linked SPICE file 'LMV339.SML'
Translated: H1 22 4 POLY(1) V1 0 748.395 -5483.95
to BH1 22 4 V=0+748.395*I(V1)+-5483.95*I(V1)*I(V1)
Translated: H2 4 21 POLY(1) V2 0 1211.03 -10110.3
to BH2 4 21 V=0+1211.03*I(V2)+-10110.3*I(V2)*I(V2)
Too few parameters for subcircuit type "LMV339" (instance: xU1:B)
FATAL: Failed to expand subcircuits.
Simulation FAILED due to fatal simulator errors.
What I'm doing wrong! I analyze other models, and they a built on the same way, I think!