assembler para 93c46
Hi,
Interconnection of SPI Master and Slave unit is done as follows:
1. Interconnect the following signals of Master and slave
MOSI to MOSI
MISO to MISO and
SCK to SCK
Connect SS- of Master to Vdd and
SS- of Slave to Vss.
2. Load SPCR of Master with 52h (sck =fosc/64) and
SPCR of Slave to 42 ; sck should be same for both.
3. Load SPIDATA of Master with the byte to be sent, it triggers SPI transmit automatically. Wait for SPIF to be set in master to find out when data transmission is over. Clear SPIF and you can load the next byte.
4. On slave Look for SPIF to be set and then read the SPIDATA and clear the SPIF bit.
5. Your slave should be ready to receive the data before the master starts its transmission, or you will lose the byte.
6. You have reversed the data assignment in the TX routine, make SPIDATA=d to load SPI reg with data 'd'
You should be able to take care of all coding aspects and correctness of the language, I will not be able to help you in this regard.
Regards,
Laktronics
Added after 30 minutes:
Hi,
Also, in SPI, only master can transmit data , so if you want to loop back the data, the Master has to do a second dummy TX and read the received data, OR, you have to change the Master/Slave roles of the devices, but synchronisation can be a problem here. Clearing of SPIF in between is important. Afterall, SPI is nothing but a back to back connected two shift registers, shifting entirely controlled by the Master.
Regards,
Laktronics