SPI Flash interface timing with controller (FPGA)

[ssundar.shan]

Hi All,
I am planning to interface a SPI flash memory with my controller (say, any FPGA).

And the controller is custom made.

Wanted to understand a bit on the how to check the timings for both the Slave (SPI flash) and the Master (Controller)? Which should be higher and which should be lower?

We know that the controller is the one providing the clock to the slave (single slave system).
Which should be higher, Master-MISO (set up time, hold time) or Slave -MISO (set up time, hold time)?

For the custom made controller, i can get the clock frequency, MISO set up time, MISO hold time and the output delay.

Lets have a example

Controller
MOSI output is -6 to 10 ns --> What is the parameter that i have to look into SPI flash
MISO set up time is 16ns -->MISO set up time of SPI flash should be higher or lower than 16ns?
MISO hold time is 0 ns -->MISO set up time of SPI flash should be higher or lower than 0ns?


Thanks in advance for help

 

[KlausST]

Hi,

usually the datasheet values are unambiguous.
There should be a timing diagram and timing specifications - usually in a table.
Please show us the datasheet.

Klaus

 

[ssundar.shan]

Thx for response.

My controller values are below
And the SPI flash part is W25Q16DVSSIG


Thanks for your help.

 

[KlausST]

Hi,

You say FPGA, but give an SPI specification...
This means the SPI interface is not compiled HDL code. Can you confirm this?
Is this the FPGA configuration interface?

It says "after Reset" at the clock frequency... thus I assume it can be adjusted. Did you adjust anything, or is it running with the default parameters?

General SPI:
The most critical thing you have to take care when you want to operate an SPI slave with an SPI master are:
* SPI clock frequency
* SPI mode
If both match then you have a good chance that the interface is working correctly.
(You don't have lenthy wiring or other semiconductors (like buffers) in the SPI signal wires?)

How I usually do checks like this:
* I print out timing diagram and timing value tables of both devices.
* then I use the slave data and go item by item through them comparing with the master data.
Usually the values of the master are narrow, while the slave just gives it's limits as "min" or "max".

Maybe the slave says" clock frequency max = 50MHz"
And the master says typ. 3.125MHz
--> then you are on the safe side.

Klaus