SPI during Vdd disable

Hello all,

I'm designing a system in which two peripherals are interfaced to a MCU via SPI communication. These devices (a memory IC and a wifi module) will be used rarely (roughly 6x/ea per month), so in an effort to minimize power consumption, separate rails providing power to each device will be enabled only during use to forego quiescent current in ~enable modes. So I suppose my first question is whether this is a good idea.

Assuming this scheme is workable, my question is how the mosi/miso/clk lines will impact a device not being powered. As an example, there may be instances when the wifi shield is used while the memory IC rail is disabled, causing shared data lines to drive pins on the unpowered device. Is this an issue or do SPI devices take this scenario into account?

To correct this potential problem I have included a series resistor and connected to each shared data line a Schottky between the pin and the respective rail. Is this an acceptable way to handle it?

Thank you for your input.

Hello!

I don't think it is a good idea, All these items (Wifi module, spi flash or so) have a low power
mode. At least all the recent devices I know. I agree that low power is not no power. However,
whatever you do, your control logic (the logic that powers your devices) will consume power.
Now of course, you can add another level: a switch that would power the switch that would
power your devices....

Dora.

You could do it but only if the SPI lines can be held low when the chips are powered down so you don't turn on the internal protection diodes. This means the SPI lines cannot be shared. You could add some logic between the microcontroller and the peripheral SPI to force the lines low when not used.

Keith

Keith,

That was my thought as well. What do you think of the strategy I described above, with protection Schottkys at the pins tied to the rail? My concern is whether the high frequency content introduced into the supply line will lead to unexpected behavior. I have not worked with SPI devices in the past and am unsure of their sensitivity. I'm using an 8 MHz (max) SPI clock.

-Matt

I don't think there is a big risk of blowing up the devices - the problem is power consumption. You are disabling the devices to minimise power but will end up powering it through the I/O lines through the Schottkys. There is the risk of slowing the edges and causing problems due to the resistors, as you say, but you will also be loading the SPI lines as they will be powering the device. It isn't a good solution.

Keith

Alot of SPI devices has a sleep mode. Maybe this could be the answer?

ojz0r said:

Alot of SPI devices has a sleep mode. Maybe this could be the answer?

Click to expand...

I'll see what real power differences exist between the two methods. It looks like this is the safer approach. Thanks for your help.

-Matt