There are a number of things wrong with your code that I can see. However some of those might be due to the OP not posting the code originally within the 'code' tags so I would strongly suggest that the OP check to make sure they code is as they have it.
First off is a design issue: I would strongly recommend that you use the \SS\ pin for the salve and drive this accordingly from the master. This will prevent any stray transition on the SCK from completely messing up all further exchanges.
Secondly, both the master and the slave have CKP and CKE as 0. Look carefully at Figures 10-2 and 10-3 and I think you will see that you need to set SMP to 0. If it is set to 1 (as you have it) then you will be sampling right at the time the data is transitioning from one bit to the next.
I can see where you set the SCK pin to be an input for the 'slave' but there is nothing that sets the SCK pin to be an output for the 'master'. (There does seem to be duplicated code where you set the 'swccw' value twice.) Remember the default for the TRISx registers is to set the pin to be an input. Further I can;t see code where you set the SDO pin to output in either apps.
In your 'master' code I can't see where you actually write to the SPI buffer. That is what is required to start the exchange.
In the 'slave' code you don't wait to check that you have received anything from the 'master' but just grab whatever is in the SSPBUF every time. (Don't rely on delays as you can easily get the master and the slave out of sync with each other.) At best you will get whatever was exchanged from the master last time and at worst you will get random garbage. You need to wait for the BF bit to be set before you read from the buffer.
Also you seem to be using the SPI module as a UART where the master simply sends off something and the slave is expected to receive it. That is (almost) how a UART works but not how the SPI module works. The SPI is an *exchange* protocol where the save puts a value into the SSPBUF and then waits for the master to initiate the exchange. When the master write to its SSPBUF, the master and slave exchange their values (with the master driving the clock and therefore the speed of the exchange) and both then set their BF bit high when the exchange completes. At that point BOTH the master and the slave are expected to read the SSPBUF (which resets the BF bit) - if the slave doesn't read the buffer by the time the next exchange occurs, then the SSPOV bit will be set and slave will ignore all further exchanges until it is cleared by your software.
Given all that, as
@barry says, we don;t know what your actual problem is. However I suspect that you have not even got anything passed from the master to the slave because of all of the above issues. Therefore they may well be other problems with your code that you have yet to find.
Susan