SPI Bus noise reduction, any ideas?

spi bus length

I have a number of boards that communicate to about 10 different SPI connected devices, all on the same bus. 1 of these happens to be an Atmel DataFlash. The DataFlash appears to be experiencing a corrupted memory problem. These boards exist in fairly noisy environments and the PCB track length of the SPI bus can be about 20cm in total length.

(1) Are there any "rule of thumb" techniques that I can use when laying out the PCB to minimise noise pickup? Maybe surround each signal line of the SPI Bus with a ground line? Ensure that the ground plane runs underneath all of the SPI lines? Trying to create some sheilding here. If I have a multilayer board, maybe the SPI lines should go on an inner layer with a ground plane/zone/thick track running above and below them.

(2) What about bus termination since it is probably behaving more like a transmission line. I have seen an example in Motorola's engineering bulletion EB393/D which has an example of SPI Bus termination and decoupling, but this only refers to one device connected to the bus.

Appreciate any ideas.Thanks.

It sounds like you actually know yourself what to do you just want someone to confirm it.
I would definitely suspect that your lines need some kind of termination on the clock and probably data lines. Have you looked at both of these lines on your scope. Is there substantial ringing which could cause an erroneous clock signal or large ringing on the data line to cause the wrong logic to be clocked through.

Your thoughts on PCB layout are all good high frequency techniques but are more valid for analog signals that are susceptible to crosstalk/pickup. The one thing I would recommend is the use of a ground plane and make sure that the SPI lines run over an uninterrupted reference plane wherever possible.

Hope this helps.