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SPEED UP VERILOG SIMULATION WITHOUT SPENDING A PENNY

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foster_cn

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speed up verilog simulation

good paper
 

speeding up verilog simulations

A recent paper,
suggested a very interesting trick: "Many complex tests require
initializing configuration registers and memories to a known
state. Many times using regular tasks to perform writes and reads to
verify operations can consume 10-50% of total test time. Initializing
registers and memories in bulk can save this time."
 

Please re-upload
 

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