speed limits on tsmc standard cell libraries

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rakko

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has anyone here ever used the standard cells in tsmc libraries in high speed designs? tsmc libraries are characterized for a top speed of around 600 mhz but realistically these cells can run much faster some libraries can even run twice as fast as the rated speed. the trick is to simulate and check timing by some other method such as spice simulations rather than primetime. my questions are; 1- based on your experience, is this possible? 2- how would you go about undertaking this task? 3- any other tools beside spice which can help me with this?
 

becareful!!!
everything depends on your layout
the extracted netlist will generally be 50% to 70% of the original, pre-extraction, spice performance.
 

yes
manual layout can give a high speed.such cpu of intel the core is manual layout
 

sometime the process is a key element for wire delay connecnted among std cells,such as ,0.18u should take much concern about wire delay than 0.25um.so their may have different limited speed.
 

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