spectreVerilog has error (Error! Line is too long - being truncated [verilog-ltlt])

[leonel.mendoza]

spectreVerilog has error below:
Error! Line is too long - being truncated [Verilog-LTLT]
"saveDefs", 939:

Error! sysntax error [Verilog]
"textfixture.template", 36:endmodule<-

How can I fix the above errror?

Anyone can help?? Pls.