Specify delay regs manually or by parameters in Verilog?

[korgull]

verilog specify

Hi,
I am currently modeling an AES design with a 256-bit key. My dilemma is that I have a case where the key expansion pipeline is quicker than the pipeline which does the actual encryption. I have an example in VHDL to which the author parameterized the delay for the key expansion so that it matches the encryption pipeline and each generated key arrives at the proper time during the addRoundKey cycle.

Now, I do not see an easy way to do this in Verilog, so I have been manually specifying registers as I need them and tap off to the encryption rounds when I need it:

// Key Expansion Delay circuits
        delayReg128 D0 (.IN(KEY[127:0]), .CLK(CLOCK), .OUT(KEYDLY0));
        delayReg128 D1 (.IN(KEYDLY0), .CLK(CLOCK), .OUT(KEYDLY1));
        delayReg256 D2 (.IN(KXP1), .CLK(CLOCK), .OUT(KEYDLY2));
        delayReg128 D3 (.IN(KEYDLY2[255:128]), .CLK(CLOCK), .OUT(KEYDLY3));
        delayReg128 D4 (.IN(KEYDLY2[127:0]), .CLK(CLOCK), .OUT(KEYDLY4));
        delayReg128 D5 (.IN(KEYDLY4), .CLK(CLOCK), .OUT(KEYDLY5));
        delayReg128 D6 (.IN(KEYDLY5), .CLK(CLOCK), .OUT(KEYDLY6));
        delayReg256 D7 (.IN(KXP2), .CLK(CLOCK), .OUT(KEYDLY7));
        [blah.. blah. blah..

Is there an easier way to do this that I am not aware of? Or is this how it is done in Verilog?

thanks!

 

[tarkyss]

specify in verilog

I am not sure I understand your question correctly
I think there are several ways to solve it, for example
1, specify delay in your RTL code, which is only for behavior simulation, while set constraint when you synthesis, so DC can insert delay cell in the path
2, calculate the delay and how much delay cell or buffer will be needed, and add delay cell or buffer directly in your RTL just as what is done in your VHDL example

 

[deva_eda]

clock delay verilog

Hi,

I think you can do this even in verilog.

1. Similar like vhdl you can parametrize the delay values.
2. Other way to deal with this is pass the key expansion signals through a long chain of buffers squentially. Lets say pass them through a buffer chain of length 30. Now make a case case statement to choose different delay values. let say for sel is the selection line. For sel "00" pickup the key expansion signal that is passed through 0 buffers(i.e no delay). For sel "01" pickup the key expansion signal that is passed through 10 buffers. For sel "10" pickup the key expansion signal that is passed through 20 buffers. For sel "11" pickup the key expansion signal that is passed through 30 buffers.

Hope this helps

 

[pete_lu]

verilog clock delay

I think you need to add the delay regs manually.
And remember "set_dont_touch" to these delay regs, or they can disappear after synthesis. You can write single verilog codes for simulation like this:
`ifdef funcsim
assign #100 a = b;
`else
delayReg ...
...
...
`endif