specification of POR (Power On Reset)

[jianjing526]

spec of POR

As is known to all, POR(power on reset) circuit is used to reset other circuits. variation resulted from process-voltage-temperature always appears wild. Under certain conditions excellent POR can be designed. But how to make the spec of POR? Can any buddy lend me a help? Thanks in advance!

 

[ankitgarg0312]

Re: spec of POR

normal specs of por can be:

1. minimum reset pulse width to ensure proper reset for chip
2. when vdd goes up,threshold above which reset pulse should be asserted
3. if vdd goes down for some time interval (glitch), reset pulse should be reasserted
4. power consumption after reset function has been done

 

[jianjing526]

Thanks, how long to reset a normal size digital circuit, several microseconds?

 

[tyanata]

Main characteristc of every POR is VDD level at which POR releases.
Another important characteristics are Hysteresis levels (if available), and
current consumption, in general when certain chip is in sleep mode only part which consumes is POR so it is important to be with low current consumption.

 

[ankitgarg0312]

Reset pulse signal have to travel inside chip , for long traces of metal it may happen that pulse width gets reduced so use buffers to ensure proper reset width on all parts of chip

POR that i designed had a reset pulse width of 10us (minimum) across all corners.

 

[jianjing526]

Thanks to all!
Reset pulse width( Treset ) variation from pvt simulation is too wild to control, especially when the power on time ranges from 10u to 10m. 10us reset pulse may be enough for resetting digital block. But if the pulse width is several 100ms, is there any potential failure besides the IC settles slowly?

 

[ankitgarg0312]

hmmm...

10us to 10ms variation across pvt...
which technology node are u working on ???

this much wide variation does not look to be acceptable in terms of specifications....

this much long reset pulse will make start time of your ic to be very long, which will not be acceptable ..
except this i don't think so there can be any failure in ic

u may need to revise your architecture as well to look for counterbalancing this variation effects