XoioX
Newbie level 3
Hi everyone,
I am going through a piece of code (in Verilog and converting it to VHDL) and although I can simulate it to check what it does, I'd like to make sure I understand the principle behind this line
InputComEncoded = InputCom[3] ? 2'b00 : 2'b10;
Where InputComEncoded and InputCom are defined as:
input [3:0] InputCom;
reg [1:0] InputComEncoded
Am I right to think that InputCom[3] only refers to 1 bit (MSB) of InputCom?
In which case, what is really going on when I compare a 2 bit word with a single bit signal?
When using this conditional statement: A = B ? m : n
Am I right to think that if A = B then A = m else A = n ?
Thanks for your help
(yes I am very new with Verilog! ;-) )
I am going through a piece of code (in Verilog and converting it to VHDL) and although I can simulate it to check what it does, I'd like to make sure I understand the principle behind this line
InputComEncoded = InputCom[3] ? 2'b00 : 2'b10;
Where InputComEncoded and InputCom are defined as:
input [3:0] InputCom;
reg [1:0] InputComEncoded
Am I right to think that InputCom[3] only refers to 1 bit (MSB) of InputCom?
In which case, what is really going on when I compare a 2 bit word with a single bit signal?
When using this conditional statement: A = B ? m : n
Am I right to think that if A = B then A = m else A = n ?
Thanks for your help
(yes I am very new with Verilog! ;-) )