Spartan 6 on two layer PCB

I know on some Xilinx forums this question was already discussed and conclusion is 2 layer PCB with Spartan 6 is asking for problems. I have project where is ARM processor and also needs some "fast" state machine to handle operation. I have wrote and tested preliminary version of VHDL code, it uses about 100 flip-flops and fit inside larger CoolRunner2 CPLD chip. Our suppliers are suggesting to change this CoolRunner to Spartan 6, because XILINX is increasing prices and increasing minimal quantities of orders of devices from older series. I could agree, to choose Spartan 6 chip, even if the smallest device will be use only 10% of chip resources, but according to whole project specification, 2 layer PCB must be used. In my design FPGA will be clocked aroung 10MHz, switched signal will be up to 1MHz, about 10 pins of programmable device will be used, will NOT use any magic blocks like memory interfaces, MGT, differential lines, DCGs, etc. Do you think Spartan 6 could be used on 2 layer PCB in such simple design?

Maybe it will work. Maybe not. You can try and pour a lot of ground plane on the bottom layer . But you could also look at using a different PLD, you don't have to use a Spartan; you could use something like a Lattice ICE40. But CPLD or FPGA, without a ground plane you're not creating a particularly robust design.

you should consider switching to lattice or microsemi if you aren't using any of those "magic" resources. They make quite a few small FPGA devices and something like a microsemi nano devices could be used on a 2 layer board without too much of a problem. They are also a lot cheaper than the Xilinx Spartan or CoolRunner2.

I agree with ads-ee, a Spartan 6 is complete overkill for your application. Lattice is probably your best choice for a small and easy to use FPGA. Stay away from Microsemi though, their design tools are mediocre and the support and documentation is very limited!

That said, at 10 MHz you won't have to worry about high speed issues that typically require a 4 layer board to fix. A BGA can be a problem on 2 layer boards, because routing the power traces will be tricky. You may be able to solve this issue by choosing the pins on the outside of the package for IO, and pouring a power plane on top and a ground plane on bottom layer. Make sure to add sufficient 100nF decoupling caps to the bottom side of the board!

We don't know whether the design is high speed or not.... What are the rise times of the signals...
4 layers is not a fix its the bare minimum for digital designs these days taking all the requirements into consideration... EMC, Signal Integrity etc. anything less is crazy these days...

marce said:

We don't know whether the design is high speed or not.... What are the rise times of the signals...
4 layers is not a fix its the bare minimum for digital designs these days taking all the requirements into consideration... EMC, Signal Integrity etc. anything less is crazy these days...

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Right, it's not just the frequency, it's the rise time; at least as far as EMI is concerned. But the ringing caused by fast edges and impedance mismatch will not be as big a problem for lower frequencies; it is still not optimal, though.

There's been no mention of what the end use of this board is: is it for production or just a one-of-a-kind hobbyist thing? If it's for production, you better make sure you test it properly before you release it. If it's a hobby thing, then go ahead and use two layers and hope for the best.

elektryk said:

In my design FPGA will be clocked aroung 10MHz, switched signal will be up to 1MHz, about 10 pins of programmable device will be used,

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marce said:

We don't know whether the design is high speed or not.... What are the rise times of the signals...

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barry said:

Right, it's not just the frequency, it's the rise time; at least as far as EMI is concerned. But the ringing caused by fast edges and impedance mismatch will not be as big a problem for lower frequencies; it is still not optimal, though.

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The frequencies were stated in the OP's 1st post. 10 MHz clock with 1 MHz signal switching (I'm assuming at the device pins).

I would suggest running the I/O with the minimum drive strength of 4mA or 2mA (if available). This will slow down the rise time as there won't be a large amount of current supplied by the output driver, that should alleviate most of the problems with fast rise times and EMI. It will also reduce the effects of impedance mismatch as it will limit the amount of high frequency components in the signal.

Read what I put to reiterate....
We don't know whether the design is high speed or not.... What are the rise times of the signals...
That is what determines whether a design is high speed or not (rise time)..... We gathered what the frequencies were.

No ground plane just some copper pours on a two layer design, impedances will be all over the place. But I do agree lowest drive strength possible, and if necessary add series termination resistors.....