Spartan 6 generate out of phase clocks

[knicklicht]

Hello all,

I am currently trying to get the verilog-ethernet project (https://github.com/alexforencich/verilog-ethernet) to run on my Spartan 6 xc6slx16. My PHY is connected via RGMII and the MAC uses two 125MHz clocks 90 degrees out of phase. As an input I have a 25Mhz clock. While there is a sample project for RGMII it uses a Virtex 6 and MMCM which is not available on the Spartan.
I have tried using a PLL to generate the two clocks but I don't get a response from the board when sending a UDP message. Assuming that I didn't make a mistake elsewhere could the PLL be the issue and do I need two chained DLLs? Does anyone know of an example that shows how to do this properly? The Xilinx Application Note 174 ("Using Delay-Locked Loops in Spartan-II/IIE FPGAs") only shows how to chain two DLLs to multiply clocks by 4. Here is my current PLL code (generated by the clock wizard):

wire        clkout0;
wire        clkout1;
wire        clkout2_unused;
wire        clkout3_unused;
wire        clkout4_unused;
wire        clkout5_unused;
wire        clkfbout;
wire        clkfbout_buf;
wire        pll_locked;

IBUFG
clk_ibufg_inst(
    .I(clk),
    .O(clk_ibufg)
);

PLL_BASE
#(.BANDWIDTH              ("OPTIMIZED"),
    .CLK_FEEDBACK           ("CLKFBOUT"),
    .COMPENSATION           ("SYSTEM_SYNCHRONOUS"),
    .DIVCLK_DIVIDE          (1),
    .CLKFBOUT_MULT          (20),
    .CLKFBOUT_PHASE         (0.000),
    .CLKOUT0_DIVIDE         (4),
    .CLKOUT0_PHASE          (0.000),
    .CLKOUT0_DUTY_CYCLE     (0.500),
    .CLKOUT1_DIVIDE         (4),
    .CLKOUT1_PHASE          (90.000),
    .CLKOUT1_DUTY_CYCLE     (0.500),
    .CLKIN_PERIOD           (40.000),
    .REF_JITTER             (0.010))
pll_base_inst
    // Output clocks
(   .CLKFBOUT              (clkfbout),
    .CLKOUT0               (clkout0),
    .CLKOUT1               (clkout1),
    .CLKOUT2               (clkout2_unused),
    .CLKOUT3               (clkout3_unused),
    .CLKOUT4               (clkout4_unused),
    .CLKOUT5               (clkout5_unused),
    // Status and control signals
    .LOCKED                (pll_locked),
    .RST                   (1'b0),
    // Input clock control
    .CLKFBIN               (clkfbout_buf),
    .CLKIN                 (clk_ibufg));


// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
    .I (clkfbout));

BUFG clkout1_buf
(.O   (clk_int),
    .I   (clkout0));

BUFG clkout2_buf
(.O   (clk90_int),
    .I   (clkout1));

sync_reset #(
    .N(4)
)
sync_reset_inst (
    .clk(clk_int),
    //.rst(~dcm_locked),
    .rst(~pll_locked),
    .out(rst_int)
);

 

[barry]

Ethernet is extremely complex. your problem could be your PLL or a million other things. Why don’t you just verify 5he two clocks?

 

[dpaul]

Assuming that I didn't make a mistake elsewhere could the PLL be the issue and do I need two chained DLLs?

Did you do a simulation of your design?
Can your design transmit and receive raw Ethernet frames through the RGMII interface?
(Xilinx has example designs to help, you just need to adapt it for the board you are using).

An RGMII is a relatively difficult to debug interface and I would say first ascertain that you have functionally verified your design through simulation.

 

[FvM]

Regarding PLL operation, you noticed that AN 174 is related to old Spartan II technique. Spartan 6 has full featured PLL with individual phase adjustment per clock output. No problem in general to get phase shifted clocks.

Don't want to guess about function of your MAC core.