spartan 3e reset problem

[sujithchakra]

spartan 3e reset

Hi,

My design has modules like i2c controller, cpu, sram, gpio. I
integrated all the above modules. This design is implemented in
Spartan 3e based Digilent Basys board. The design when triggered,
reads data from the externally connected I2C EEPROM, copies into SRAM
in the design and then triggers the cpu to process the data and output
the result on to the leds on board.

When I configure the FPGA with the bit file(write the bit file into
ROM on board/FPGA), the design works fine for the first time but when
I push the FPGA reset button to reconfigure the FPGA, the design does
not work. When I power the whole board off, wait for some time and
then repeat the process, it works fine only for the first time.

I tested the board with a simple counter and it is working fine. Does
my design need a different treatment because it uses an externally
connected I2C EEPROM?

Please help.

Thanks.

 

[tom_hanks]

spartan 3e power on reset

when u receive a reset signal in FPGA..
Which fuction will get run...

are you reseting the I2C eeprom as well from FPGA...

Cheers,
Tom

 

[sujithchakra]

resetting spartan 3e

Hi Tom,

I am talking about the whole FPGA being reset in order to reload my design into FPGA again, not my design in the FPGA...I2C EEPROM(24XX256) does not have a reset pin on it.....here is the data sheet of EEPROM I am using...

https://ww1.microchip.com/downloads/en/devicedoc/21203M.pdf

Thanks for your response

 

[radix]

spartan3e reset

sujithchakra,

Do you know if the FPGA reset signal is asynchronous or synchronous?

Also, how are you coding your resets for your functional blocks (asynchronous or synchronous)?

It may be possible that everything resets fine when the circuit comes out of reset at power-up, but not later when internal nodes have values other than the power-up values. This problem may appear if there is significant skew on the reset line across the chip and some nodes come out of reset a clock cycle later than other nodes.

You made need to add a circuit like Figure 9 which is described in:

http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf

Example 8b in the paper above has the vhdl for the reset circuit.

Radix

 

[teja321]

“reset” button on the xilinx spartan3e

Pushing a reset button doesn't reconfigure the FPGA.

The reset switch mostly would be connected to a single pin of the FPGA. U can use this as an asynchronous reset to reset ur state m/c or other use.

To reconfigure the FPGA u have to power on/off the FPGA/board.