Spartan 3E development tools on Linux

#!/bin/bash

. /opt/xilinx/ise_144/14.4/ISE_DS/settings32.sh

export DISPLAY=:0

ise $@

#!/bin/sh

echo "++++++++++++++++++++++++++++++"
echo "+ Cleans old generated files +"
echo "++++++++++++++++++++++++++++++"
rm -rf xst/work

echo "++++++++++++++++++++++++++++++++++++++++++++++++++++++"
echo "+ Translates Verilog $1.vl to generic netlist $1.ngc +"
echo "++++++++++++++++++++++++++++++++++++++++++++++++++++++"
echo "run -ifn $1.vl -ifmt Verilog -ofn $1.ngc -p xc3s500e-pq208 -opt_mode Speed -opt_level 1" | xst

echo "++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"
echo "+Translates the netlist $1.ngc to native FPGA elements and takes into account pin assignment from the $1.ucf +"
echo "++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"
ngdbuild -p xc3s500e-pq208 -uc $1.ucf $1.ngc

echo "+++++++++++++++++++++++++++++++++++++++++++++++++++++"
echo "+ Translates it to elements of the specified target +"
echo "+++++++++++++++++++++++++++++++++++++++++++++++++++++"
map -detail -pr b $1.ngd

echo "++++++++++++++++++++++++"
echo "+ Place and route step +"
echo "++++++++++++++++++++++++"
par -ol high -w $1.ncd $1.par.ncd

echo "+++++++++++++++++++++++++++++++++++++++++++++++++++"
echo "+ Generates the $1.bit file to configure the FPGA +"
echo "+++++++++++++++++++++++++++++++++++++++++++++++++++"
bitgen -w -g StartupClk:Cclk $1.par.ncd $1.bit


echo "+++++++++++++++++++++++++++++++++++++++++++++++++++++++"
echo "+ Translates $1.bit to a form suitable to the eeproms +"
echo "+++++++++++++++++++++++++++++++++++++++++++++++++++++++"
# promgen -w -p mcs -o $1.mcs -u 0 $1.bit

echo "++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"
echo "+  (or split in two pieces to two EEPROM chips of smaller size on this board)  +" 
echo "++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"
#promgen -w -x xcf04s xcf04s -p mcs -o $1.mcs -u 0 $1.bit

module counter(CLEAR, CK12, LED);
input CLEAR;
input CK12;
output [7:0] LED;

reg[27:00] count;
reg metaclear;

always @(posedge CK12)
begin
  metaclear <= CLEAR;
  if(metaclear)
    count <= 0;
  else
   count <= count + 1;
end

assign LED = count[27:20];

endmodule

NET "CLEAR"  LOC ="P13" ; # BUTON 1
NET "CK12"   LOC ="P39" ; # 12.5 Mhz clock
NET "LED<0>" LOC ="P70" ; # LED 0 
NET "LED<1>" LOC ="P71" ; # LED 1
NET "LED<2>" LOC ="P62" ; # LED 2
NET "LED<3>" LOC ="P66" ; # LED 3
NET "LED<4>" LOC ="P67" ; # LED 4
NET "LED<5>" LOC ="P68" ; # LED 5
NET "LED<6>" LOC ="P63" ; # LED 6
NET "LED<7>" LOC ="P65" ; # LED 7

 ./comp_fpga.sh test1

++++++++++++++++++++++++++++++
+ Cleans old generated files +
++++++++++++++++++++++++++++++

++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ Translates Verilog test1.vl to generic netlist test1.ngc +
++++++++++++++++++++++++++++++++++++++++++++++++++++++
Release 14.5 - xst P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
--> 
WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution
   for the specified device family. You are free to use it in order to take
   advantage of its enhanced HDL parsing/elaboration capabilities. However,
   please be aware that you may be impacted by  language support differences.
   This version may also result in circuit performance and device utilization
   differences for your particular design. You can always revert back to the
   default XST solution by setting the "use_new_parser" option to value "no" 
   on the XST command line or in the XST process properties panel.

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "test1.vl"
Input Format                       : Verilog

---- Target Parameters
Output File Name                   : "test1.ngc"
Target Device                      : xc3s500e-pq208

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "test1.vl" into library work
Parsing module <counter>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <counter>.
WARNING:HDLCompiler:413 - "test1.vl" Line 15: Result of 29-bit expression is truncated to fit in 28-bit target.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <counter>.
    Related source file is "/home/yannoo/Devel/FPGA/test1.vl".
    Found 28-bit register for signal <count>.
    Found 1-bit register for signal <metaclear>.
    Found 28-bit adder for signal <count[27]_GND_1_o_add_1_OUT> created at line 15.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  29 D-type flip-flop(s).
Unit <counter> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 28-bit adder                                          : 1
# Registers                                            : 2
 1-bit register                                        : 1
 28-bit register                                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <counter>.
The following registers are absorbed into counter <count>: 1 register on signal <count>.
Unit <counter> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 28-bit up counter                                     : 1
# Registers                                            : 1
 Flip-Flops                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <counter> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 0) on block counter, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 29
 Flip-Flops                                            : 29

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : test1.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 85
#      GND                         : 1
#      INV                         : 1
#      LUT1                        : 27
#      MUXCY                       : 27
#      VCC                         : 1
#      XORCY                       : 28
# FlipFlops/Latches                : 29
#      FD                          : 1
#      FDR                         : 28
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 9
#      IBUF                        : 1
#      OBUF                        : 8

Device utilization summary:
---------------------------

Selected Device : 3s500epq208-5 

 Number of Slices:                       15  out of   4656     0%  
 Number of Slice Flip Flops:             29  out of   9312     0%  
 Number of 4 input LUTs:                 28  out of   9312     0%  
 Number of IOs:                          10
 Number of bonded IOBs:                  10  out of    158     6%  
 Number of GCLKs:                         1  out of     24     4%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CK12                               | BUFGP                  | 29    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 4.294ns (Maximum Frequency: 232.910MHz)
   Minimum input arrival time before clock: 1.731ns
   Maximum output required time after clock: 4.063ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CK12'
  Clock period: 4.294ns (frequency: 232.910MHz)
  Total number of paths / destination ports: 434 / 56
-------------------------------------------------------------------------
Delay:               4.294ns (Levels of Logic = 28)
  Source:            count_1 (FF)
  Destination:       count_27 (FF)
  Source Clock:      CK12 rising
  Destination Clock: CK12 rising

  Data Path: count_1 to count_27
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.514   0.509  count_1 (count_1)
     LUT1:I0->O            1   0.612   0.000  Mcount_count_cy<1>_rt (Mcount_count_cy<1>_rt)
     MUXCY:S->O            1   0.404   0.000  Mcount_count_cy<1> (Mcount_count_cy<1>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<2> (Mcount_count_cy<2>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<3> (Mcount_count_cy<3>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<4> (Mcount_count_cy<4>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<5> (Mcount_count_cy<5>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<6> (Mcount_count_cy<6>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<7> (Mcount_count_cy<7>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<8> (Mcount_count_cy<8>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<9> (Mcount_count_cy<9>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<10> (Mcount_count_cy<10>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<11> (Mcount_count_cy<11>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<12> (Mcount_count_cy<12>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<13> (Mcount_count_cy<13>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<14> (Mcount_count_cy<14>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<15> (Mcount_count_cy<15>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<16> (Mcount_count_cy<16>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<17> (Mcount_count_cy<17>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<18> (Mcount_count_cy<18>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<19> (Mcount_count_cy<19>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<20> (Mcount_count_cy<20>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<21> (Mcount_count_cy<21>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<22> (Mcount_count_cy<22>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<23> (Mcount_count_cy<23>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<24> (Mcount_count_cy<24>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<25> (Mcount_count_cy<25>)
     MUXCY:CI->O           0   0.051   0.000  Mcount_count_cy<26> (Mcount_count_cy<26>)
     XORCY:CI->O           1   0.699   0.000  Mcount_count_xor<27> (Result<27>)
     FDR:D                     0.268          count_27
    ----------------------------------------
    Total                      4.294ns (3.785ns logic, 0.509ns route)
                                       (88.1% logic, 11.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CK12'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              1.731ns (Levels of Logic = 1)
  Source:            CLEAR (PAD)
  Destination:       metaclear (FF)
  Destination Clock: CK12 rising

  Data Path: CLEAR to metaclear
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.106   0.357  CLEAR_IBUF (CLEAR_IBUF)
     FD:D                      0.268          metaclear
    ----------------------------------------
    Total                      1.731ns (1.374ns logic, 0.357ns route)
                                       (79.4% logic, 20.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CK12'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              4.063ns (Levels of Logic = 1)
  Source:            count_27 (FF)
  Destination:       LED<7> (PAD)
  Source Clock:      CK12 rising

  Data Path: count_27 to LED<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.514   0.380  count_27 (count_27)
     OBUF:I->O                 3.169          LED_7_OBUF (LED<7>)
    ----------------------------------------
    Total                      4.063ns (3.683ns logic, 0.380ns route)
                                       (90.6% logic, 9.4% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock CK12
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CK12           |    4.294|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 15.00 secs
Total CPU time to Xst completion: 15.23 secs
 
WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution
   for the specified device family. You are free to use it in order to take
   advantage of its enhanced HDL parsing/elaboration capabilities. However,
   please be aware that you may be impacted by  language support differences.
   This version may also result in circuit performance and device utilization
   differences for your particular design. You can always revert back to the
   default XST solution by setting the "use_new_parser" option to value "no" 
   on the XST command line or in the XST process properties panel.
--> 


Total memory usage is 108800 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    0 (   0 filtered)

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+Translates the netlist test1.ngc to native FPGA elements and takes into account pin assignment from the test1.ucf +
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Release 14.5 - ngdbuild P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Command Line: /opt/Xilinx/14.5/ISE_DS/ISE/bin/lin/unwrapped/ngdbuild -p
xc3s500e-pq208 -uc test1.ucf test1.ngc

Reading NGO file "/home/yannoo/Devel/FPGA/test1.ngc" ...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "test1.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "test1.ngd" ...
Total REAL time to NGDBUILD completion:  9 sec
Total CPU time to NGDBUILD completion:   9 sec

Writing NGDBUILD log file "test1.bld"...

NGDBUILD done.

+++++++++++++++++++++++++++++++++++++++++++++++++++++
+ Translates it to elements of the specified target +
+++++++++++++++++++++++++++++++++++++++++++++++++++++
Release 14.5 - Map P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
Using target part "3s500epq208-5".
WARNING:Map:34 - Speed grade not specified.  Using default "-5".
Mapping design into LUTs...
ERROR:MapLib:30 - LOC constraint P13 on CLEAR is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P67 on LED<4> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P66 on LED<3> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P70 on LED<0> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :   4
Number of warnings :   1

+++++++++++++++++++++++++++++++++++++++++++++++++++
+ Generates the test1.bit file to configure the FPGA +
+++++++++++++++++++++++++++++++++++++++++++++++++++
Release 14.5 - Bitgen P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

+++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ Translates test1.bit to a form suitable to the eeproms +
+++++++++++++++++++++++++++++++++++++++++++++++++++++++

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+  (or split in two pieces to two EEPROM chips of smaller size on this board)  +
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

ERROR:MapLib:30 - LOC constraint P13 on CLEAR is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P67 on LED<4> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P66 on LED<3> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P70 on LED<0> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

NET "CLEAR"  LOC ="P13" ; # BUTON 1
NET "CK12"   LOC ="P39" ; # 12.5 Mhz clock
NET "LED<0>" LOC ="P70" ; # LED 0 
NET "LED<1>" LOC ="P71" ; # LED 1
NET "LED<2>" LOC ="P62" ; # LED 2
NET "LED<3>" LOC ="P66" ; # LED 3
NET "LED<4>" LOC ="P67" ; # LED 4
NET "LED<5>" LOC ="P68" ; # LED 5
NET "LED<6>" LOC ="P63" ; # LED 6
NET "LED<7>" LOC ="P65" ; # LED 7

# Makefile to compile and download a simple Verilog program

#DEVICE=xc3s100e-4-vq100
DEVICE=xc3s500e-pq208

default: counter.bin

counter.ngc: counter.vl
	echo "run -ifn counter.vl -ifmt Verilog -ofn counter -p \
	$(DEVICE) -opt_mode Speed -opt_level 1" | xst

counter.ngd: counter.ngc counter.ucf
	ngdbuild -p $(DEVICE) -uc counter.ucf counter.ngc

counter.ncd: counter.ngd
	map -k 6 -detail -pr b counter.ngd

counter.pcf: counter.ngd
	map -k 6 -detail -pr b counter.ngd

parout.ncd: counter.ncd
	par counter.ncd parout.ncd counter.pcf

counter.bit: parout.ncd
	bitgen -g CRC:Enable -g StartUpClk:CClk -g Compress parout.ncd counter.bit counter.pcf

counter.bin: counter.bit
	promgen -w -p bin -o counter.bin -u 0 counter.bit

install: counter.bin
	#stty --file=/dev/ttyUSB0 -opost
	#cat counter.bin > /dev/ttyUSB0
	# We want raw output

clean:
	rm -rf counter.bgn counter.bin counter.bit counter.bld \
counter.drc counter.map counter_map.xrpt counter.mrp \
counter.ncd counter.ngc counter.ngd counter_ngdbuild.xrpt \
counter.ngm counter_par.xrpt counter.pcf counter.prm \
counter_summary.xml counter_usage.xml counter_xst.xrpt \
netlist.lst parout.ncd parout.pad parout_pad.csv \
parout_pad.txt parout.par parout.ptwx parout.unroutes \
parout.xpi xlnx_auto_0.ise xlnx_auto_0_xdb xst

module counter(CLEAR, CK12, LED);
input CLEAR;
input CK12;
output [7:0] LED;

reg[27:00] count;
reg metaclear;

always @(posedge CK12)
begin
  metaclear <= CLEAR;
  if(metaclear)
    count <= 0;
  else
   count <= count + 1;
end

assign LED = count[27:20];

endmodule

NET "CLEAR"  LOC = P13 ; # BUTON 1
NET "CK12"   LOC = P39 ; # 12.5 Mhz clock
NET "LED[0]" LOC = P70 ; # LED 0 
NET "LED[1]" LOC = P71 ; # LED 1
NET "LED[2]" LOC = P62 ; # LED 2
NET "LED[3]" LOC = P66 ; # LED 3
NET "LED[4]" LOC = P67 ; # LED 4
NET "LED[5]" LOC = P68 ; # LED 5
NET "LED[6]" LOC = P63 ; # LED 6
NET "LED[7]" LOC = P65 ; # LED 7

yannoo@Ubuntoo:~/Devel/FPGA$ make 
echo "run -ifn counter.vl -ifmt Verilog -ofn counter -p \
	xc3s500e-pq208 -opt_mode Speed -opt_level 1" | xst
Release 14.5 - xst P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
--> 
WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution
   for the specified device family. You are free to use it in order to take
   advantage of its enhanced HDL parsing/elaboration capabilities. However,
   please be aware that you may be impacted by  language support differences.
   This version may also result in circuit performance and device utilization
   differences for your particular design. You can always revert back to the
   default XST solution by setting the "use_new_parser" option to value "no" 
   on the XST command line or in the XST process properties panel.

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "counter.vl"
Input Format                       : Verilog

---- Target Parameters
Output File Name                   : "counter"
Target Device                      : xc3s500e-pq208

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "counter.vl" into library work
Parsing module <counter>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <counter>.
WARNING:HDLCompiler:413 - "counter.vl" Line 15: Result of 29-bit expression is truncated to fit in 28-bit target.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <counter>.
    Related source file is "/home/yannoo/Devel/FPGA/counter.vl".
    Found 28-bit register for signal <count>.
    Found 1-bit register for signal <metaclear>.
    Found 28-bit adder for signal <count[27]_GND_1_o_add_1_OUT> created at line 15.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  29 D-type flip-flop(s).
Unit <counter> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 28-bit adder                                          : 1
# Registers                                            : 2
 1-bit register                                        : 1
 28-bit register                                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <counter>.
The following registers are absorbed into counter <count>: 1 register on signal <count>.
Unit <counter> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 28-bit up counter                                     : 1
# Registers                                            : 1
 Flip-Flops                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <counter> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 0) on block counter, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 29
 Flip-Flops                                            : 29

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : counter.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 85
#      GND                         : 1
#      INV                         : 1
#      LUT1                        : 27
#      MUXCY                       : 27
#      VCC                         : 1
#      XORCY                       : 28
# FlipFlops/Latches                : 29
#      FD                          : 1
#      FDR                         : 28
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 9
#      IBUF                        : 1
#      OBUF                        : 8

Device utilization summary:
---------------------------

Selected Device : 3s500epq208-5 

 Number of Slices:                       15  out of   4656     0%  
 Number of Slice Flip Flops:             29  out of   9312     0%  
 Number of 4 input LUTs:                 28  out of   9312     0%  
 Number of IOs:                          10
 Number of bonded IOBs:                  10  out of    158     6%  
 Number of GCLKs:                         1  out of     24     4%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CK12                               | BUFGP                  | 29    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 4.294ns (Maximum Frequency: 232.910MHz)
   Minimum input arrival time before clock: 1.731ns
   Maximum output required time after clock: 4.063ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CK12'
  Clock period: 4.294ns (frequency: 232.910MHz)
  Total number of paths / destination ports: 434 / 56
-------------------------------------------------------------------------
Delay:               4.294ns (Levels of Logic = 28)
  Source:            count_1 (FF)
  Destination:       count_27 (FF)
  Source Clock:      CK12 rising
  Destination Clock: CK12 rising

  Data Path: count_1 to count_27
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.514   0.509  count_1 (count_1)
     LUT1:I0->O            1   0.612   0.000  Mcount_count_cy<1>_rt (Mcount_count_cy<1>_rt)
     MUXCY:S->O            1   0.404   0.000  Mcount_count_cy<1> (Mcount_count_cy<1>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<2> (Mcount_count_cy<2>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<3> (Mcount_count_cy<3>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<4> (Mcount_count_cy<4>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<5> (Mcount_count_cy<5>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<6> (Mcount_count_cy<6>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<7> (Mcount_count_cy<7>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<8> (Mcount_count_cy<8>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<9> (Mcount_count_cy<9>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<10> (Mcount_count_cy<10>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<11> (Mcount_count_cy<11>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<12> (Mcount_count_cy<12>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<13> (Mcount_count_cy<13>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<14> (Mcount_count_cy<14>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<15> (Mcount_count_cy<15>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<16> (Mcount_count_cy<16>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<17> (Mcount_count_cy<17>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<18> (Mcount_count_cy<18>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<19> (Mcount_count_cy<19>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<20> (Mcount_count_cy<20>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<21> (Mcount_count_cy<21>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<22> (Mcount_count_cy<22>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<23> (Mcount_count_cy<23>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<24> (Mcount_count_cy<24>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<25> (Mcount_count_cy<25>)
     MUXCY:CI->O           0   0.051   0.000  Mcount_count_cy<26> (Mcount_count_cy<26>)
     XORCY:CI->O           1   0.699   0.000  Mcount_count_xor<27> (Result<27>)
     FDR:D                     0.268          count_27
    ----------------------------------------
    Total                      4.294ns (3.785ns logic, 0.509ns route)
                                       (88.1% logic, 11.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CK12'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              1.731ns (Levels of Logic = 1)
  Source:            CLEAR (PAD)
  Destination:       metaclear (FF)
  Destination Clock: CK12 rising

  Data Path: CLEAR to metaclear
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.106   0.357  CLEAR_IBUF (CLEAR_IBUF)
     FD:D                      0.268          metaclear
    ----------------------------------------
    Total                      1.731ns (1.374ns logic, 0.357ns route)
                                       (79.4% logic, 20.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CK12'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              4.063ns (Levels of Logic = 1)
  Source:            count_27 (FF)
  Destination:       LED<7> (PAD)
  Source Clock:      CK12 rising

  Data Path: count_27 to LED<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.514   0.380  count_27 (count_27)
     OBUF:I->O                 3.169          LED_7_OBUF (LED<7>)
    ----------------------------------------
    Total                      4.063ns (3.683ns logic, 0.380ns route)
                                       (90.6% logic, 9.4% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock CK12
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CK12           |    4.294|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 17.00 secs
Total CPU time to Xst completion: 17.07 secs
 
WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution
   for the specified device family. You are free to use it in order to take
   advantage of its enhanced HDL parsing/elaboration capabilities. However,
   please be aware that you may be impacted by  language support differences.
   This version may also result in circuit performance and device utilization
   differences for your particular design. You can always revert back to the
   default XST solution by setting the "use_new_parser" option to value "no" 
   on the XST command line or in the XST process properties panel.
--> 


Total memory usage is 102652 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ngdbuild -p xc3s500e-pq208 -uc counter.ucf counter.ngc
Release 14.5 - ngdbuild P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Command Line: /opt/Xilinx/14.5/ISE_DS/ISE/bin/lin/unwrapped/ngdbuild -p
xc3s500e-pq208 -uc counter.ucf counter.ngc

Reading NGO file "/home/yannoo/Devel/FPGA/counter.ngc" ...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "counter.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "counter.ngd" ...
Total REAL time to NGDBUILD completion:  10 sec
Total CPU time to NGDBUILD completion:   10 sec

Writing NGDBUILD log file "counter.bld"...

NGDBUILD done.
map -k 6 -detail -pr b counter.ngd
Release 14.5 - Map P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
ERROR:Portability:90 - Command line error: Switch "-k" is not allowed.

Usage: map [-bp] [-c [<packfactor:0,100>]] [-cm <covermode>] [-detail]
[-equivalent_register_removal on|off] [-global_opt off|power|speed|area]
[-global_opt7 off|power|speed|area] [-ignore_keep_hierarchy] [-intstyle
ise|xflow|silent|pa] [-ir [off|place|all]] [-ise <iseProjectFile>] [-l] [-lc
off|area|auto] [-logic_opt off|on] [-mt on|off|1|2|3|4] [-ntd] [-o
<outfile[.ncd]>] [-ol std|med|high] [-p <partname>] [-power on|off|high||xe]
[-activityfile <activityfile[.vcd|.saif]>] [-pr off|i|o|b] [-r 8|4|off]
[-register_duplication [off|on]] [-retiming off|on] [-smartguide <guide[.ncd]>]
[-t <costtable:1,100>] [-timing] [-tx on|off|aggressive|limit] [-u] [-w] [-x]
[-xe c|n] [-xt <costtable:0,5>] [-filter <filter_file[.filter]>] <infile[.ngd]>
[<prffile[.pcf]>]
make: *** [counter.ncd] Erreur 2

yannoo@Ubuntoo:~/Devel/FPGA$ make
echo "run -ifn counter.vl -ifmt Verilog -ofn counter -p \
	xc3s100e-4-vq100 -opt_mode Speed -opt_level 1" | xst
Release 14.5 - xst P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
--> 
WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution
   for the specified device family. You are free to use it in order to take
   advantage of its enhanced HDL parsing/elaboration capabilities. However,
   please be aware that you may be impacted by  language support differences.
   This version may also result in circuit performance and device utilization
   differences for your particular design. You can always revert back to the
   default XST solution by setting the "use_new_parser" option to value "no" 
   on the XST command line or in the XST process properties panel.

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "counter.vl"
Input Format                       : Verilog

---- Target Parameters
Output File Name                   : "counter"
Target Device                      : xc3s100e-4-vq100

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "counter.vl" into library work
Parsing module <counter>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <counter>.
WARNING:HDLCompiler:413 - "counter.vl" Line 15: Result of 29-bit expression is truncated to fit in 28-bit target.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <counter>.
    Related source file is "/home/yannoo/Devel/FPGA/counter.vl".
    Found 28-bit register for signal <count>.
    Found 1-bit register for signal <metaclear>.
    Found 28-bit adder for signal <count[27]_GND_1_o_add_1_OUT> created at line 15.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  29 D-type flip-flop(s).
Unit <counter> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 28-bit adder                                          : 1
# Registers                                            : 2
 1-bit register                                        : 1
 28-bit register                                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <counter>.
The following registers are absorbed into counter <count>: 1 register on signal <count>.
Unit <counter> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 28-bit up counter                                     : 1
# Registers                                            : 1
 Flip-Flops                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <counter> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 0) on block counter, actual ratio is 1.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 29
 Flip-Flops                                            : 29

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : counter.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 85
#      GND                         : 1
#      INV                         : 1
#      LUT1                        : 27
#      MUXCY                       : 27
#      VCC                         : 1
#      XORCY                       : 28
# FlipFlops/Latches                : 29
#      FD                          : 1
#      FDR                         : 28
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 9
#      IBUF                        : 1
#      OBUF                        : 8

Device utilization summary:
---------------------------

Selected Device : 3s100evq100-4 

 Number of Slices:                       15  out of    960     1%  
 Number of Slice Flip Flops:             29  out of   1920     1%  
 Number of 4 input LUTs:                 28  out of   1920     1%  
 Number of IOs:                          10
 Number of bonded IOBs:                  10  out of     66    15%  
 Number of GCLKs:                         1  out of     24     4%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CK12                               | BUFGP                  | 29    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 4.941ns (Maximum Frequency: 202.388MHz)
   Minimum input arrival time before clock: 1.946ns
   Maximum output required time after clock: 4.310ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CK12'
  Clock period: 4.941ns (frequency: 202.388MHz)
  Total number of paths / destination ports: 434 / 56
-------------------------------------------------------------------------
Delay:               4.941ns (Levels of Logic = 28)
  Source:            count_1 (FF)
  Destination:       count_27 (FF)
  Source Clock:      CK12 rising
  Destination Clock: CK12 rising

  Data Path: count_1 to count_27
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.591   0.595  count_1 (count_1)
     LUT1:I0->O            1   0.704   0.000  Mcount_count_cy<1>_rt (Mcount_count_cy<1>_rt)
     MUXCY:S->O            1   0.464   0.000  Mcount_count_cy<1> (Mcount_count_cy<1>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<2> (Mcount_count_cy<2>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<3> (Mcount_count_cy<3>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<4> (Mcount_count_cy<4>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<5> (Mcount_count_cy<5>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<6> (Mcount_count_cy<6>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<7> (Mcount_count_cy<7>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<8> (Mcount_count_cy<8>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<9> (Mcount_count_cy<9>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<10> (Mcount_count_cy<10>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<11> (Mcount_count_cy<11>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<12> (Mcount_count_cy<12>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<13> (Mcount_count_cy<13>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<14> (Mcount_count_cy<14>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<15> (Mcount_count_cy<15>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<16> (Mcount_count_cy<16>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<17> (Mcount_count_cy<17>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<18> (Mcount_count_cy<18>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<19> (Mcount_count_cy<19>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<20> (Mcount_count_cy<20>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<21> (Mcount_count_cy<21>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<22> (Mcount_count_cy<22>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<23> (Mcount_count_cy<23>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<24> (Mcount_count_cy<24>)
     MUXCY:CI->O           1   0.059   0.000  Mcount_count_cy<25> (Mcount_count_cy<25>)
     MUXCY:CI->O           0   0.059   0.000  Mcount_count_cy<26> (Mcount_count_cy<26>)
     XORCY:CI->O           1   0.804   0.000  Mcount_count_xor<27> (Result<27>)
     FDR:D                     0.308          count_27
    ----------------------------------------
    Total                      4.941ns (4.346ns logic, 0.595ns route)
                                       (88.0% logic, 12.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CK12'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              1.946ns (Levels of Logic = 1)
  Source:            CLEAR (PAD)
  Destination:       metaclear (FF)
  Destination Clock: CK12 rising

  Data Path: CLEAR to metaclear
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.218   0.420  CLEAR_IBUF (CLEAR_IBUF)
     FD:D                      0.308          metaclear
    ----------------------------------------
    Total                      1.946ns (1.526ns logic, 0.420ns route)
                                       (78.4% logic, 21.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CK12'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              4.310ns (Levels of Logic = 1)
  Source:            count_27 (FF)
  Destination:       LED<7> (PAD)
  Source Clock:      CK12 rising

  Data Path: count_27 to LED<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.591   0.447  count_27 (count_27)
     OBUF:I->O                 3.272          LED_7_OBUF (LED<7>)
    ----------------------------------------
    Total                      4.310ns (3.863ns logic, 0.447ns route)
                                       (89.6% logic, 10.4% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock CK12
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CK12           |    4.941|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 16.74 secs
 
WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution
   for the specified device family. You are free to use it in order to take
   advantage of its enhanced HDL parsing/elaboration capabilities. However,
   please be aware that you may be impacted by  language support differences.
   This version may also result in circuit performance and device utilization
   differences for your particular design. You can always revert back to the
   default XST solution by setting the "use_new_parser" option to value "no" 
   on the XST command line or in the XST process properties panel.
--> 


Total memory usage is 102660 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ngdbuild -p xc3s100e-4-vq100 -uc counter.ucf counter.ngc
Release 14.5 - ngdbuild P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Command Line: /opt/Xilinx/14.5/ISE_DS/ISE/bin/lin/unwrapped/ngdbuild -p
xc3s100e-4-vq100 -uc counter.ucf counter.ngc

Reading NGO file "/home/yannoo/Devel/FPGA/counter.ngc" ...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "counter.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "counter.ngd" ...
Total REAL time to NGDBUILD completion:  13 sec
Total CPU time to NGDBUILD completion:   12 sec

Writing NGDBUILD log file "counter.bld"...

NGDBUILD done.
#map -k 6 -detail -pr b counter.ngd
map -detail -pr b counter.ngd
Release 14.5 - Map P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
Using target part "3s100evq100-4".
Mapping design into LUTs...
Writing file counter.ngm...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
Writing design file "counter.ncd"...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:            28 out of   1,920    1%
  Number of 4 input LUTs:                 1 out of   1,920    1%
Logic Distribution:
  Number of occupied Slices:             14 out of     960    1%
    Number of Slices containing only related logic:      14 out of      14 100%
    Number of Slices containing unrelated logic:          0 out of      14   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:          28 out of   1,920    1%
    Number used as logic:                 1
    Number used as a route-thru:         27

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

  Number of bonded IOBs:                 10 out of      66   15%
    IOB Flip Flops:                       1
  Number of BUFGMUXs:                     1 out of      24    4%

Average Fanout of Non-Clock Nets:                1.83

Peak Memory Usage:  156 MB
Total REAL time to MAP completion:  6 secs 
Total CPU time to MAP completion:   6 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "counter.mrp" for details.
par counter.ncd parout.ncd counter.pcf
Release 14.5 - par P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.



Constraints file: counter.pcf.
Loading device for application Rf_Device from file '3s100e.nph' in environment /opt/Xilinx/14.5/ISE_DS/ISE/.
   "counter" is an NCD, version 3.2, device xc3s100e, package vq100, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRODUCTION 1.27 2013-03-26".


Design Summary Report:

 Number of External IOBs                          10 out of 66     15%

   Number of External Input IOBs                  2

      Number of External Input IBUFs              2
        Number of LOCed External Input IBUFs      2 out of 2     100%


   Number of External Output IOBs                 8

      Number of External Output IOBs              8
        Number of LOCed External Output IOBs      8 out of 8     100%


   Number of External Bidir IOBs                  0


   Number of BUFGMUXs                        1 out of 24      4%
   Number of Slices                         14 out of 960     1%
      Number of SLICEMs                      0 out of 480     0%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 3 secs 
Finished initial Timing Analysis.  REAL time: 3 secs 


Starting Placer
Total REAL time at the beginning of Placer: 3 secs 
Total CPU  time at the beginning of Placer: 3 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:20d7429e) REAL time: 6 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:20d7429e) REAL time: 6 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:20d7429e) REAL time: 6 secs 

Phase 4.2  Initial Clock and IO Placement

Phase 4.2  Initial Clock and IO Placement (Checksum:21e8a286) REAL time: 6 secs 

Phase 5.30  Global Clock Region Assignment
Phase 5.30  Global Clock Region Assignment (Checksum:21e8a286) REAL time: 6 secs 

Phase 6.36  Local Placement Optimization
Phase 6.36  Local Placement Optimization (Checksum:21e8a286) REAL time: 6 secs 

Phase 7.8  Global Placement
..
Phase 7.8  Global Placement (Checksum:2a6241a5) REAL time: 11 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:2a6241a5) REAL time: 11 secs 

Phase 9.18  Placement Optimization
Phase 9.18  Placement Optimization (Checksum:33f962d4) REAL time: 11 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:33f962d4) REAL time: 11 secs 

Total REAL time to Placer completion: 11 secs 
Total CPU  time to Placer completion: 11 secs 
Writing design to file parout.ncd



Starting Router


Phase  1  : 81 unrouted;      REAL time: 14 secs 

Phase  2  : 65 unrouted;      REAL time: 14 secs 

Phase  3  : 2 unrouted;      REAL time: 14 secs 

Phase  4  : 3 unrouted; (Par is working to improve performance)     REAL time: 14 secs 

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 14 secs 

Updating file: parout.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 14 secs 

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 15 secs 

Updating file: parout.ncd with current fully routed design.

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 15 secs 

Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 15 secs 

Phase 10  : 0 unrouted; (Par is working to improve performance)     REAL time: 15 secs 

Phase 11  : 0 unrouted; (Par is working to improve performance)     REAL time: 15 secs 

Phase 12  : 0 unrouted; (Par is working to improve performance)     REAL time: 15 secs 

Total REAL time to Router completion: 15 secs 
Total CPU time to Router completion: 14 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|          CK12_BUFGP |  BUFGMUX_X2Y0| No   |   15 |  0.005     |  0.045      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net CK1 | SETUP       |         N/A|     4.537ns|     N/A|           0
  2_BUFGP                                   | HOLD        |     1.565ns|            |       0|           0
----------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
   constraint is not analyzed due to the following: No paths covered by this 
   constraint; Other constraints intersect with this constraint; or This 
   constraint was disabled by a Path Tracing Control. Please run the Timespec 
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 16 secs 
Total CPU time to PAR completion: 15 secs 

Peak Memory Usage:  142 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file parout.ncd



PAR done!
bitgen -g CRC:Enable -g StartUpClk:CClk -g Compress parout.ncd counter.bit counter.pcf
Release 14.5 - Bitgen P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '3s100e.nph' in environment
/opt/Xilinx/14.5/ISE_DS/ISE/.
   "counter" is an NCD, version 3.2, device xc3s100e, package vq100, speed -4
Opened constraints file counter.pcf.

Sun May 26 18:46:03 2013

Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "counter.bit".
Bitstream compression saved 418784 bits.
Bitstream generation is complete.
promgen -w -p bin -o counter.bin -u 0 counter.bit
Release 14.5 - Promgen P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
0x4e3c (20028) bytes loaded up from 0x0
Using generated prom size of 32K
Writing file "counter.bin".
Writing file "counter.prm".
Writing file "counter.cfi".

...
map -detail -pr b counter.ngd
Release 14.5 - Map P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
Using target part "3s500epq208-5".
WARNING:Map:34 - Speed grade not specified.  Using default "-5".
Mapping design into LUTs...
ERROR:MapLib:30 - LOC constraint P13 on CLEAR is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P67 on LED<4> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P66 on LED<3> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint P70 on LED<0> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :   4
Number of warnings :   1
make: *** [counter.ncd] Erreur 2

ERROR:MapLib:30 - LOC constraint XXXX on YYYY  is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

RCXQ208_V5_1.1 Pin list								
Signal name	I/O	Pin number	Signal name	I/O	Pin number	Signal name	I/O	Pin number
Globale reset								
RESET			Tact Switch					
SPI port	I	6	KEY_LINE0 (K2)	I	57	VGA		
SPI_CLK	O	8	KEY_LINE1 (K3)	I	58	H_SYNC	O	140
SPI_CS	0	9	KEY_LINE2 (K4)	I	71	V_SYNC	O	144
SPI_MOSI	0	11	KEY_LINE3 (K5)	I	72	R	O	147
SPI_MISO	I	12	KEY_LINE4 (K6)	I	91	G	O	146
UART			KEY_LINE5 (K7)	I	101	B	O	145
UART_RX	I	14	KEY_LINE6 (K8)	I	110			
UART_TX	0	15	2 Global clock in			PS2		
RTC DS1302			CLK_50M	I	80	PS2_DATA	I	148
RTC_CLK	O	19	CLK_40M	I	82	PS2_CLK	I	159
RTC_IO	IO	18						
RTC_RST	O	16	TEMP(DS18B20)	IO	98	SRAM		
DIP Switch			LCD1602_D0,TUBE_D0	O	102	SRAM_D0	IO	190
PUSH_SW1	I	20	LCD1602_D1,TUBE_D1	O	99	SRAM_D1	IO	189
PUSH_SW2	I	26	LCD1602_D2,TUBE_D2	O	107	SRAM_D2	IO	187
PUSH_SW3	I	32	LCD1602_D3,TUBE_D3	O	109	SRAM_D3	IO	186
PUSH_SW4	I	43	LCD1602_D4,TUBE_D4	O	112	SRAM_D4	IO	185
PUSH_SW5	I	51	LCD1602_D5,TUBE_D5	O	100	SRAM_D5	IO	181
PUSH_SW6	I	54	LCD1602_D6,TUBE_D6	O	106	SRAM_D6	IO	180
LEDs			LCD1602_D7,TUBE_D7	O	108	SRAM_D7	IO	179
LED2	O	22	LCD1602_E	O	113	SRAM_D8	IO	162
LED3	O	23	LCD1602_RW	O	115	SRAM_D9	IO	163
LED4	O	24	LCD1602_RS	O	116	SRAM_D10	IO	164
LED5	O	25	IR RECEIVER			SRAM_D11	IO	165
LED6	O	28	IR	I	118	SRAM_D12	IO	202
LED7	O	29	BUZZER(PWM drive)			SRAM_D13	IO	203
J6			BUZZER	O	119	SRAM_D14	IO	205
GPIO_0 (SCL)J6.40	IO	30				SRAM_D15	IO	206
GPIO_1 (SDA)J6.39	O	31	TUBE_EN0	O	132			
GPIO_2  --- J6.38	IO	33	TUBE_EN1	O	129			
GPIO_3  --- J6.37	IO	34	TUBE_EN2	O	128	SRAM_A0	O	200
GPIO_4  --- J6.36	IO	35	TUBE_EN3	O	127	SRAM_A1	O	199
GPIO_5  --- J6.35	IO	36	TUBE_EN4	O	126	SRAM_A2	O	197
GPIO_6  --- J6.34	IO	39	TUBE_EN5	O	123	SRAM_A3	O	196
GPIO_7  --- J6.33	IO	40	TUBE_EN6	O	122	SRAM_A4	O	193
GPIO_8  --- J6.32	IO	41	TUBE_EN7	O	120	SRAM_A5	O	177
GPIO_9  --- J6.31	IO	42	ADC TLC549			SRAM_A6	O	172
GPIO_10 --- J6.30	IO	45	ADC_CLK	O	139	SRAM_A7	O	171
GPIO_11 --- J6.29	IO	47	ADC_DO	I	138	SRAM_A8	O	168
GPIO_12 --- J6.28	IO	48	ADC_CS	O	137	SRAM_A9	O	167
GPIO_13 --- J6.27	IO	49	DAC TLC5615C			SRAM_A10	O	150
GPIO_14 --- J6.26	IO	50	DAC_DIN	O	135	SRAM_A11	O	151
GPIO_15 --- J6.25	IO	55	DAC_CLK	O	134	SRAM_A12	O	152
GPIO_16 --- J6.24	IO	60	DAC_CS	O	133	SRAM_A13	O	153
GPIO_17 --- J6.23	IO	61	J7			SRAM_A14	O	160
GPIO_18 --- J6.22	IO	62	INPUT_0 -- J7.3	I	124	SRAM_A15	O	3
GPIO_19 --- J6.21	IO	63	INPUT_1 -- J7.4	I	130	SRAM_A16	O	4
GPIO_20 --- J6.20	IO	64	INPUT_2 -- J7.5	I	136	SRAM_A17	O	5
GPIO_21 --- J6.19	IO	65	INPUT_3 -- J7.6	I	142	SRAM_A18(IS61LV51216)	O	161
GPIO_22 --- J6.18	IO	68	INPUT_4 -- J7	I	194			
GPIO_23 --- J6.17	IO	69	INPUT_5 -- J8	I	154	SRAM_WE	O	178
GPIO_24 --- J6.16	IO	74	INPUT_6 -- J9	I	204	SRAM_OE	O	2
GPIO_25 --- J6.15	IO	75	INPUT_7 -- J10	I	169	SRAM_CS	O	192
GPIO_26 --- J6.14	IO	76	INPUT_8 -- J11	I	174			
GPIO_27 --- J6.13	IO	77	INPUT_9 -- J12	I	175			
GPIO_28 --- J6.12	IO	78	INPUT_10 -- J13	I	183			
GPIO_29 --- J6.11	IO	83	INPUT_11 -- J14	I	184			
GPIO_30 --- J6.10	IO	89						
GPIO_31 --- J6.9	IO	90						
GPIO_32 --- J6.8	IO	93						
GPIO_33 --- J6.7	IO	94						
GPIO_34 --- J6.6	IO	96						
GPIO_35 --- J6.5	IO	97

NET "CLEAR"  LOC = "P13" ; # BUTON 1
NET "CK12"   LOC = "P39" ; # 12.5 Mhz clock

#NET "LED[0]" LOC = "??" ; # LED 0 
#NET "LED[1]" LOC = "??" ; # LED 1
NET "LED[2]" LOC = "22" ; # LED 2
NET "LED[3]" LOC = "23" ; # LED 3
NET "LED[4]" LOC = "24" ; # LED 4
NET "LED[5]" LOC = "25" ; # LED 5
NET "LED[6]" LOC = "26" ; # LED 6
NET "LED[7]" LOC = "27" ; # LED

map -detail -pr b counter.ngd
Release 14.5 - Map P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
Using target part "3s500epq208-5".
WARNING:Map:34 - Speed grade not specified.  Using default "-5".
Mapping design into LUTs...
ERROR:MapLib:30 - LOC constraint P13 on CLEAR is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint 27 on LED<7> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint 26 on LED<6> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint 25 on LED<5> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint 24 on LED<4> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint 23 on LED<3> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint 22 on LED<2> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :   7
Number of warnings :   1
make: *** [counter.ncd] Erreur 2

-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
P1|||PROG_B||||||||||||
P2|SRAM_OE|IOB|IO_L01P_3|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P3|SRAM_ADDR<15>|IOB|IO_L01N_3|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P4|SRAM_ADDR<16>|IOB|IO_L02P_3|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P5|SRAM_ADDR<17>|IOB|IO_L02N_3/VREF_3|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P6|RST_B|IBUF|IP|INPUT|LVCMOS33|3||||NONE||LOCATED|NO|NONE|
P7|||VCCAUX||||||||2.5||||
P8||DIFFM|IO_L03P_3|UNUSED||3|||||||||
P9||DIFFS|IO_L03N_3|UNUSED||3|||||||||
P10|||GND||||||||||||
P11||DIFFM|IO_L04P_3|UNUSED||3|||||||||
P12||DIFFS|IO_L04N_3|UNUSED||3|||||||||
P13|||VCCINT||||||||1.2||||
P14|UART_RX_I|IBUF|IP|INPUT|LVCMOS33|3||||NONE||LOCATED|NO|NONE|
P15|UART_TX_O|IOB|IO_L05P_3|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P16|RTC_RST|IOB|IO_L05N_3|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P17|||GND||||||||||||
P18|RTC_IO|IOB|IO_L06P_3|BIDIR|LVCMOS33|3|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P19|RTC_CLK|IOB|IO_L06N_3|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P20|PUSH_SW1|IBUF|IP/VREF_3|INPUT|LVCMOS33|3||||NONE||LOCATED|NO|NONE|
P21|||VCCO_3|||3|||||3.30||||
P22|LED_DATA<0>|IOB|IO_L07P_3/LHCLK0|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P23|LED_DATA<1>|IOB|IO_L07N_3/LHCLK1|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P24|LED_DATA<2>|IOB|IO_L08P_3/LHCLK2|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P25|LED_DATA<3>|IOB|IO_L08N_3/LHCLK3/IRDY2|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P26|PUSH_SW2|IBUF|IP|INPUT|LVCMOS33|3||||NONE||LOCATED|NO|NONE|
P27|||GND||||||||||||
P28|LED_DATA<4>|IOB|IO_L09P_3/LHCLK4/TRDY2|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P29|LED_DATA<5>|IOB|IO_L09N_3/LHCLK5|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P30|SCL|IOB|IO_L10P_3/LHCLK6|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P31|SDA|IOB|IO_L10N_3/LHCLK7|BIDIR|LVCMOS33|3|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P32|PUSH_SW3|IBUF|IP|INPUT|LVCMOS33|3||||NONE||LOCATED|NO|NONE|
P33||DIFFM|IO_L11P_3|UNUSED||3|||||||||
P34||DIFFS|IO_L11N_3|UNUSED||3|||||||||
P35||DIFFM|IO_L12P_3|UNUSED||3|||||||||
P36||DIFFS|IO_L12N_3|UNUSED||3|||||||||
P37|||GND||||||||||||
P38|||VCCO_3|||3|||||3.30||||
P39||DIFFM|IO_L13P_3|UNUSED||3|||||||||
P40||DIFFS|IO_L13N_3|UNUSED||3|||||||||
P41||DIFFM|IO_L14P_3|UNUSED||3|||||||||
P42||DIFFS|IO_L14N_3|UNUSED||3|||||||||
P43|PUSH_SW4|IBUF|IP|INPUT|LVCMOS33|3||||NONE||LOCATED|NO|NONE|
P44|||VCCAUX||||||||2.5||||
P45||IOB|IO/VREF_3|UNUSED||3|||||||||
P46|||VCCO_3|||3|||||3.30||||
P47||DIFFM|IO_L15P_3|UNUSED||3|||||||||
P48||DIFFS|IO_L15N_3|UNUSED||3|||||||||
P49||DIFFM|IO_L16P_3|UNUSED||3|||||||||
P50|DISP|IOB|IO_L16N_3|OUTPUT|LVCMOS33|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
P51|PUSH_SW5|IBUF|IP|INPUT|LVCMOS33|3||||NONE||LOCATED|NO|NONE|
P52|||GND||||||||||||
P53|||GND||||||||||||
P54|PUSH_SW6|IBUF|IP|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P55|HSYNC|IOB|IO_L01P_2/CSO_B|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P56||DIFFS|IO_L01N_2/INIT_B|UNUSED||2|||||||||
P57|K2|IBUF|IP_L02P_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P58|K3|IBUF|IP_L02N_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P59|||VCCO_2|||2|||||3.30||||
P60|VSYNC|IOB|IO_L03P_2/DOUT/BUSY|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P61|DEN|IOB|IO_L03N_2/MOSI/CSI_B|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P62|DCLK|IOB|IO_L04P_2|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P63|RGB_DATA<4>|IOB|IO_L04N_2|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P64|IN_PIN|IBUF|IO_L05P_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P65|RGB_DATA<3>|IOB|IO_L05N_2|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P66|||VCCAUX||||||||2.5||||
P67|||VCCINT||||||||1.2||||
P68|RGB_DATA<2>|IOB|IO_L06P_2|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P69|RGB_DATA<1>|IOB|IO_L06N_2|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P70|||GND||||||||||||
P71|K4|IBUF|IP_L07P_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P72|K5|IBUF|IP_L07N_2/VREF_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P73|||VCCO_2|||2|||||3.30||||
P74|RGB_DATA<0>|IOB|IO_L08P_2/D7/GCLK12|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P75|RGB_DATA<10>|IOB|IO_L08N_2/D6/GCLK13|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P76|RGB_DATA<9>|IOB|IO/D5|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P77|RGB_DATA<8>|IOB|IO_L09P_2/D4/GCLK14|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P78|RGB_DATA<7>|IOB|IO_L09N_2/D3/GCLK15|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P79|||GND||||||||||||
P80|SYSCLK_50M|IBUF|IP_L10P_2/RDWR_B/GCLK0|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P81||DIFFSI|IP_L10N_2/M2/GCLK1|UNUSED||2|||||||||
P82|SYSCLK_40M|IBUF|IO_L11P_2/D2/GCLK2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P83|RGB_DATA<6>|IOB|IO_L11N_2/D1/GCLK3|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P84||IOB|IO/M1|UNUSED||2|||||||||
P85|||GND||||||||||||
P86||DIFFM|IO_L12P_2/M0|UNUSED||2|||||||||
P87||DIFFS|IO_L12N_2/DIN/D0|UNUSED||2|||||||||
P88|||VCCO_2|||2|||||3.30||||
P89|RGB_DATA<5>|IOB|IO_L13P_2|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P90|RGB_DATA<15>|IOB|IO_L13N_2|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P91|K6|IBUF|IP|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P92|||VCCAUX||||||||2.5||||
P93|RGB_DATA<14>|IOB|IO_L14P_2/A23|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P94|RGB_DATA<13>|IOB|IO_L14N_2/A22|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P95|||GND||||||||||||
P96|RGB_DATA<12>|IOB|IO_L15P_2/A21|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P97|RGB_DATA<11>|IOB|IO_L15N_2/A20|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P98|TEMP_IO|IOB|IO/VREF_2|BIDIR|LVCMOS33|2|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P99|TUBE_LCD1602_DATA_BUS<1>|IOB|IO_L16P_2/VS2/A19|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P100|TUBE_LCD1602_DATA_BUS<5>|IOB|IO_L16N_2/VS1/A18|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P101|K7|IBUF|IP|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE|
P102|TUBE_LCD1602_DATA_BUS<0>|IOB|IO_L17P_2/VS0/A17|OUTPUT|LVCMOS33|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
P103||DIFFS|IO_L17N_2/CCLK|UNUSED||2|||||||||
P104|||DONE||||||||||||
P105|||GND||||||||||||
P106|TUBE_LCD1602_DATA_BUS<6>|IOB|IO_L01P_1/A16|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P107|TUBE_LCD1602_DATA_BUS<2>|IOB|IO_L01N_1/A15|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P108|TUBE_LCD1602_DATA_BUS<7>|IOB|IO_L02P_1/A14|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P109|TUBE_LCD1602_DATA_BUS<3>|IOB|IO_L02N_1/A13|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P110|K8|IBUF|IP|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P111|||VCCAUX||||||||2.5||||
P112|TUBE_LCD1602_DATA_BUS<4>|IOB|IO_L03P_1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P113|LCD_EN|IOB|IO_L03N_1/VREF_1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P114|||VCCO_1|||1|||||3.30||||
P115|LCD_WR|IOB|IO_L04P_1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P116|LCD_RS|IOB|IO_L04N_1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P117|||VCCINT||||||||1.2||||
P118|IR_IO|IBUF|IP|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P119|BUZZER|IOB|IO_L05P_1/A12|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P120|TUBE_SEL<4>|IOB|IO_L05N_1/A11|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P121|||GND||||||||||||
P122|TUBE_SEL<5>|IOB|IO_L06P_1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P123|TUBE_SEL<6>|IOB|IO_L06N_1/VREF_1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P124||IBUF|IP|UNUSED||1|||||||||
P125|||VCCO_1|||1|||||3.30||||
P126|TUBE_SEL<7>|IOB|IO_L07P_1/A10/RHCLK0|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P127|TUBE_SEL<0>|IOB|IO_L07N_1/A9/RHCLK1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P128|TUBE_SEL<1>|IOB|IO_L08P_1/A8/RHCLK2|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P129|TUBE_SEL<2>|IOB|IO_L08N_1/A7/RHCLK3/TRDY1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P130||IBUF|IP|UNUSED||1|||||||||
P131|||GND||||||||||||
P132|TUBE_SEL<3>|IOB|IO_L09P_1/A6/RHCLK4/IRDY1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P133|DAC_CS|IOB|IO_L09N_1/A5/RHCLK5|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P134|DAC_CLK|IOB|IO_L10P_1/A4/RHCLK6|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P135|DAC_DIN|IOB|IO_L10N_1/A3/RHCLK7|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P136||IBUF|IP/VREF_1|UNUSED||1|||||||||
P137|ADC_CS|IOB|IO_L11P_1/A2|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P138|ADC_DATA|IBUF|IO_L11N_1/A1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P139|ADC_CLK|IOB|IO_L12P_1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P140|VGA_HS|IOB|IO_L12N_1/A0|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P141|||GND||||||||||||
P142||IBUF|IP|UNUSED||1|||||||||
P143|||VCCO_1|||1|||||3.30||||
P144|VGA_VS|IOB|IO_L13P_1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P145|VGA_B|IOB|IO_L13N_1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P146|VGA_G|IOB|IO_L14P_1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P147|VGA_R|IOB|IO_L14N_1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P148|PS2_DAT|IBUF|IP|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE|
P149|||VCCAUX||||||||2.5||||
P150|SRAM_ADDR<10>|IOB|IO_L15P_1/HDC|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P151|SRAM_ADDR<11>|IOB|IO_L15N_1/LDC0|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P152|SRAM_ADDR<12>|IOB|IO_L16P_1/LDC1|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P153|SRAM_ADDR<13>|IOB|IO_L16N_1/LDC2|OUTPUT|LVCMOS33|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
P154||IBUF|IP|UNUSED||1|||||||||
P155|||TMS||||||||||||
P156|||GND||||||||||||
P157|||TDO||||||||||||
P158|||TCK||||||||||||
P159|PS2_CLK|IBUF|IP|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
P160|SRAM_ADDR<14>|IOB|IO_L01P_0|OUTPUT|LVCMOS33|0|12|SLOW|NONE**|||LOCATED|NO|NONE|
P161||DIFFS|IO_L01N_0|UNUSED||0|||||||||
P162|SRAM_DATA<8>|IOB|IO_L02P_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P163|SRAM_DATA<9>|IOB|IO_L02N_0/VREF_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P164|SRAM_DATA<10>|IOB|IO_L03P_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P165|SRAM_DATA<11>|IOB|IO_L03N_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P166|||VCCAUX||||||||2.5||||
P167|SRAM_ADDR<9>|IOB|IO_L04P_0|OUTPUT|LVCMOS33|0|12|SLOW|NONE**|||LOCATED|NO|NONE|
P168|SRAM_ADDR<8>|IOB|IO_L04N_0/VREF_0|OUTPUT|LVCMOS33|0|12|SLOW|NONE**|||LOCATED|NO|NONE|
P169||IBUF|IP|UNUSED||0|||||||||
P170|||VCCINT||||||||1.2||||
P171|SRAM_ADDR<7>|IOB|IO_L05P_0|OUTPUT|LVCMOS33|0|12|SLOW|NONE**|||LOCATED|NO|NONE|
P172|SRAM_ADDR<6>|IOB|IO_L05N_0|OUTPUT|LVCMOS33|0|12|SLOW|NONE**|||LOCATED|NO|NONE|
P173|||GND||||||||||||
P174||DIFFMI|IP_L06P_0|UNUSED||0|||||||||
P175||DIFFSI|IP_L06N_0|UNUSED||0|||||||||
P176|||VCCO_0|||0|||||3.30||||
P177|SRAM_ADDR<5>|IOB|IO_L07P_0/GCLK4|OUTPUT|LVCMOS33|0|12|SLOW|NONE**|||LOCATED|NO|NONE|
P178|SRAM_WE|IOB|IO_L07N_0/GCLK5|OUTPUT|LVCMOS33|0|12|SLOW|NONE**|||LOCATED|NO|NONE|
P179|SRAM_DATA<7>|IOB|IO/VREF_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P180|SRAM_DATA<6>|IOB|IO_L08P_0/GCLK6|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P181|SRAM_DATA<5>|IOB|IO_L08N_0/GCLK7|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P182|||GND||||||||||||
P183||DIFFMI|IP_L09P_0/GCLK8|UNUSED||0|||||||||
P184||DIFFSI|IP_L09N_0/GCLK9|UNUSED||0|||||||||
P185|SRAM_DATA<4>|IOB|IO_L10P_0/GCLK10|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P186|SRAM_DATA<3>|IOB|IO_L10N_0/GCLK11|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P187|SRAM_DATA<2>|IOB|IO|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P188|||GND||||||||||||
P189|SRAM_DATA<1>|IOB|IO_L11P_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P190|SRAM_DATA<0>|IOB|IO_L11N_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P191|||VCCO_0|||0|||||3.30||||
P192|SRAM_CS|IOB|IO_L12P_0|OUTPUT|LVCMOS33|0|12|SLOW|NONE**|||LOCATED|NO|NONE|
P193|SRAM_ADDR<4>|IOB|IO_L12N_0/VREF_0|OUTPUT|LVCMOS33|0|12|SLOW|NONE**|||LOCATED|NO|NONE|
P194||IBUF|IP|UNUSED||0|||||||||
P195|||VCCAUX||||||||2.5||||
P196|SRAM_ADDR<3>|IOB|IO_L13P_0|OUTPUT|LVCMOS33|0|12|SLOW|NONE**|||LOCATED|NO|NONE|
P197|SRAM_ADDR<2>|IOB|IO_L13N_0|OUTPUT|LVCMOS33|0|12|SLOW|NONE**|||LOCATED|NO|NONE|
P198|||GND||||||||||||
P199|SRAM_ADDR<1>|IOB|IO_L14P_0|OUTPUT|LVCMOS33|0|12|SLOW|NONE**|||LOCATED|NO|NONE|
P200|SRAM_ADDR<0>|IOB|IO_L14N_0/VREF_0|OUTPUT|LVCMOS33|0|12|SLOW|NONE**|||LOCATED|NO|NONE|
P201|||VCCO_0|||0|||||3.30||||
P202|SRAM_DATA<12>|IOB|IO_L15P_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P203|SRAM_DATA<13>|IOB|IO_L15N_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P204||IBUF|IP|UNUSED||0|||||||||
P205|SRAM_DATA<14>|IOB|IO_L16P_0|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P206|SRAM_DATA<15>|IOB|IO_L16N_0/HSWAP|BIDIR|LVCMOS33|0|12|SLOW|NONE**|NONE||LOCATED|NO|NONE|
P207|||TDI||||||||||||
P208|||GND||||||||||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|

NET "CLEAR"  LOC = "P20" ; # BUTON 1
#NET "CK12"   LOC = "??" ; #  14.5 Mhz clock

NET "LED<0>" LOC = "P22" ; # LED 0 
NET "LED<1>" LOC = "P23" ; # LED 1
NET "LED<2>" LOC = "P24" ; # LED 2
NET "LED<3>" LOC = "P25" ; # LED 3
NET "LED<4>" LOC = "P28" ; # LED 4
NET "LED<5>" LOC = "P29" ; # LED 5
#NET "LED<6>]" LOC = "??" ; # LED 6
#NET "LED<7>]" LOC = "??" ; # LED 7

yannoo@Ubuntoo:~/Devel/FPGA$ make
echo "run -ifn counter.vl -ifmt Verilog -ofn counter -p \
	xc3s500e-pq208 -opt_mode Speed -opt_level 1" | xst
Release 14.5 - xst P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
--> 
WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution
   for the specified device family. You are free to use it in order to take
   advantage of its enhanced HDL parsing/elaboration capabilities. However,
   please be aware that you may be impacted by  language support differences.
   This version may also result in circuit performance and device utilization
   differences for your particular design. You can always revert back to the
   default XST solution by setting the "use_new_parser" option to value "no" 
   on the XST command line or in the XST process properties panel.

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "counter.vl"
Input Format                       : Verilog

---- Target Parameters
Output File Name                   : "counter"
Target Device                      : xc3s500e-pq208

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "counter.vl" into library work
Parsing module <counter>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <counter>.
WARNING:HDLCompiler:413 - "counter.vl" Line 15: Result of 29-bit expression is truncated to fit in 28-bit target.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <counter>.
    Related source file is "/home/yannoo/Devel/FPGA/counter.vl".
    Found 28-bit register for signal <count>.
    Found 1-bit register for signal <metaclear>.
    Found 28-bit adder for signal <count[27]_GND_1_o_add_1_OUT> created at line 15.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  29 D-type flip-flop(s).
Unit <counter> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 28-bit adder                                          : 1
# Registers                                            : 2
 1-bit register                                        : 1
 28-bit register                                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <counter>.
The following registers are absorbed into counter <count>: 1 register on signal <count>.
Unit <counter> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 28-bit up counter                                     : 1
# Registers                                            : 1
 Flip-Flops                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <counter> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 0) on block counter, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 29
 Flip-Flops                                            : 29

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : counter.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 85
#      GND                         : 1
#      INV                         : 1
#      LUT1                        : 27
#      MUXCY                       : 27
#      VCC                         : 1
#      XORCY                       : 28
# FlipFlops/Latches                : 29
#      FD                          : 1
#      FDR                         : 28
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 9
#      IBUF                        : 1
#      OBUF                        : 8

Device utilization summary:
---------------------------

Selected Device : 3s500epq208-5 

 Number of Slices:                       15  out of   4656     0%  
 Number of Slice Flip Flops:             29  out of   9312     0%  
 Number of 4 input LUTs:                 28  out of   9312     0%  
 Number of IOs:                          10
 Number of bonded IOBs:                  10  out of    158     6%  
 Number of GCLKs:                         1  out of     24     4%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CK12                               | BUFGP                  | 29    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 4.294ns (Maximum Frequency: 232.910MHz)
   Minimum input arrival time before clock: 1.731ns
   Maximum output required time after clock: 4.063ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CK12'
  Clock period: 4.294ns (frequency: 232.910MHz)
  Total number of paths / destination ports: 434 / 56
-------------------------------------------------------------------------
Delay:               4.294ns (Levels of Logic = 28)
  Source:            count_1 (FF)
  Destination:       count_27 (FF)
  Source Clock:      CK12 rising
  Destination Clock: CK12 rising

  Data Path: count_1 to count_27
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.514   0.509  count_1 (count_1)
     LUT1:I0->O            1   0.612   0.000  Mcount_count_cy<1>_rt (Mcount_count_cy<1>_rt)
     MUXCY:S->O            1   0.404   0.000  Mcount_count_cy<1> (Mcount_count_cy<1>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<2> (Mcount_count_cy<2>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<3> (Mcount_count_cy<3>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<4> (Mcount_count_cy<4>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<5> (Mcount_count_cy<5>)
     MUXCY:CI->O           1   0.052   0.000  Mcount_count_cy<6> (Mcount_count_cy<6>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<7> (Mcount_count_cy<7>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<8> (Mcount_count_cy<8>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<9> (Mcount_count_cy<9>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<10> (Mcount_count_cy<10>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<11> (Mcount_count_cy<11>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<12> (Mcount_count_cy<12>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<13> (Mcount_count_cy<13>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<14> (Mcount_count_cy<14>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<15> (Mcount_count_cy<15>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<16> (Mcount_count_cy<16>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<17> (Mcount_count_cy<17>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<18> (Mcount_count_cy<18>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<19> (Mcount_count_cy<19>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<20> (Mcount_count_cy<20>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<21> (Mcount_count_cy<21>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<22> (Mcount_count_cy<22>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<23> (Mcount_count_cy<23>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<24> (Mcount_count_cy<24>)
     MUXCY:CI->O           1   0.051   0.000  Mcount_count_cy<25> (Mcount_count_cy<25>)
     MUXCY:CI->O           0   0.051   0.000  Mcount_count_cy<26> (Mcount_count_cy<26>)
     XORCY:CI->O           1   0.699   0.000  Mcount_count_xor<27> (Result<27>)
     FDR:D                     0.268          count_27
    ----------------------------------------
    Total                      4.294ns (3.785ns logic, 0.509ns route)
                                       (88.1% logic, 11.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CK12'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              1.731ns (Levels of Logic = 1)
  Source:            CLEAR (PAD)
  Destination:       metaclear (FF)
  Destination Clock: CK12 rising

  Data Path: CLEAR to metaclear
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.106   0.357  CLEAR_IBUF (CLEAR_IBUF)
     FD:D                      0.268          metaclear
    ----------------------------------------
    Total                      1.731ns (1.374ns logic, 0.357ns route)
                                       (79.4% logic, 20.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CK12'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              4.063ns (Levels of Logic = 1)
  Source:            count_27 (FF)
  Destination:       LED<7> (PAD)
  Source Clock:      CK12 rising

  Data Path: count_27 to LED<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.514   0.380  count_27 (count_27)
     OBUF:I->O                 3.169          LED_7_OBUF (LED<7>)
    ----------------------------------------
    Total                      4.063ns (3.683ns logic, 0.380ns route)
                                       (90.6% logic, 9.4% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock CK12
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CK12           |    4.294|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 21.62 secs
 
WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution
   for the specified device family. You are free to use it in order to take
   advantage of its enhanced HDL parsing/elaboration capabilities. However,
   please be aware that you may be impacted by  language support differences.
   This version may also result in circuit performance and device utilization
   differences for your particular design. You can always revert back to the
   default XST solution by setting the "use_new_parser" option to value "no" 
   on the XST command line or in the XST process properties panel.
--> 


Total memory usage is 102656 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ngdbuild -p xc3s500e-pq208 -uc counter.ucf counter.ngc
Release 14.5 - ngdbuild P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Command Line: /opt/Xilinx/14.5/ISE_DS/ISE/bin/lin/unwrapped/ngdbuild -p
xc3s500e-pq208 -uc counter.ucf counter.ngc

Reading NGO file "/home/yannoo/Devel/FPGA/counter.ngc" ...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "counter.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "counter.ngd" ...
Total REAL time to NGDBUILD completion:  13 sec
Total CPU time to NGDBUILD completion:   12 sec

Writing NGDBUILD log file "counter.bld"...

NGDBUILD done.
#map -k 6 -detail -pr b counter.ngd
map -detail -pr b counter.ngd
Release 14.5 - Map P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
Using target part "3s500epq208-5".
WARNING:Map:34 - Speed grade not specified.  Using default "-5".
Mapping design into LUTs...
Writing file counter.ngm...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
Writing design file "counter.ncd"...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:            28 out of   9,312    1%
  Number of 4 input LUTs:                 1 out of   9,312    1%
Logic Distribution:
  Number of occupied Slices:             14 out of   4,656    1%
    Number of Slices containing only related logic:      14 out of      14 100%
    Number of Slices containing unrelated logic:          0 out of      14   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:          28 out of   9,312    1%
    Number used as logic:                 1
    Number used as a route-thru:         27

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

  Number of bonded IOBs:                 10 out of     158    6%
    IOB Flip Flops:                       1
  Number of BUFGMUXs:                     1 out of      24    4%

Average Fanout of Non-Clock Nets:                1.83

Peak Memory Usage:  165 MB
Total REAL time to MAP completion:  8 secs 
Total CPU time to MAP completion:   8 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "counter.mrp" for details.
par counter.ncd parout.ncd counter.pcf
Release 14.5 - par P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.



Constraints file: counter.pcf.
Loading device for application Rf_Device from file '3s500e.nph' in environment /opt/Xilinx/14.5/ISE_DS/ISE/.
   "counter" is an NCD, version 3.2, device xc3s500e, package pq208, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRODUCTION 1.27 2013-03-26".


Design Summary Report:

 Number of External IOBs                          10 out of 158     6%

   Number of External Input IOBs                  2

      Number of External Input IBUFs              2
        Number of LOCed External Input IBUFs      1 out of 2      50%


   Number of External Output IOBs                 8

      Number of External Output IOBs              8
        Number of LOCed External Output IOBs      6 out of 8      75%


   Number of External Bidir IOBs                  0


   Number of BUFGMUXs                        1 out of 24      4%
   Number of Slices                         14 out of 4656    1%
      Number of SLICEMs                      0 out of 2328    0%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 5 secs 
Finished initial Timing Analysis.  REAL time: 5 secs 


Starting Placer
Total REAL time at the beginning of Placer: 5 secs 
Total CPU  time at the beginning of Placer: 5 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:3f6251) REAL time: 7 secs 

Phase 2.7  Design Feasibility Check
WARNING:Place:837 - Partially locked IO Bus is found. 
    Following components of the bus are not locked: 
   	 Comp: LED<7>
   	 Comp: LED<6>

INFO:Place:834 - Only a subset of IOs are locked. Out of 8 IOs, 6 are locked and 2 are not locked. If you would like to
   print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 
Phase 2.7  Design Feasibility Check (Checksum:3f6251) REAL time: 7 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:3f6251) REAL time: 7 secs 

Phase 4.2  Initial Clock and IO Placement
........
Phase 4.2  Initial Clock and IO Placement (Checksum:2e21c976) REAL time: 8 secs 

Phase 5.30  Global Clock Region Assignment
Phase 5.30  Global Clock Region Assignment (Checksum:2e21c976) REAL time: 8 secs 

Phase 6.36  Local Placement Optimization
Phase 6.36  Local Placement Optimization (Checksum:2e21c976) REAL time: 8 secs 

Phase 7.3  Local Placement Optimization
........
Phase 7.3  Local Placement Optimization (Checksum:2e490d20) REAL time: 8 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:2e490d20) REAL time: 8 secs 

Phase 9.8  Global Placement
......
Phase 9.8  Global Placement (Checksum:3cffa80e) REAL time: 18 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:3cffa80e) REAL time: 18 secs 

Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:2f9dbb1c) REAL time: 18 secs 

Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:2f9dbb1c) REAL time: 18 secs 

Total REAL time to Placer completion: 18 secs 
Total CPU  time to Placer completion: 17 secs 
Writing design to file parout.ncd



Starting Router


Phase  1  : 81 unrouted;      REAL time: 35 secs 

Phase  2  : 65 unrouted;      REAL time: 35 secs 

Phase  3  : 4 unrouted;      REAL time: 35 secs 

Phase  4  : 5 unrouted; (Par is working to improve performance)     REAL time: 37 secs 

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 37 secs 

Updating file: parout.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 37 secs 

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 39 secs 

Updating file: parout.ncd with current fully routed design.

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 39 secs 

Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 39 secs 

Phase 10  : 0 unrouted; (Par is working to improve performance)     REAL time: 39 secs 

Phase 11  : 0 unrouted; (Par is working to improve performance)     REAL time: 39 secs 

Phase 12  : 0 unrouted; (Par is working to improve performance)     REAL time: 39 secs 

Total REAL time to Router completion: 39 secs 
Total CPU time to Router completion: 37 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|          CK12_BUFGP | BUFGMUX_X2Y10| No   |   15 |  0.012     |  0.159      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net CK1 | SETUP       |         N/A|     3.960ns|     N/A|           0
  2_BUFGP                                   | HOLD        |     1.360ns|            |       0|           0
----------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
   constraint is not analyzed due to the following: No paths covered by this 
   constraint; Other constraints intersect with this constraint; or This 
   constraint was disabled by a Path Tracing Control. Please run the Timespec 
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 41 secs 
Total CPU time to PAR completion: 38 secs 

Peak Memory Usage:  157 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 1
Number of info messages: 2

Writing design to file parout.ncd



PAR done!
bitgen -g CRC:Enable -g StartUpClk:CClk -g Compress parout.ncd counter.bit counter.pcf
Release 14.5 - Bitgen P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '3s500e.nph' in environment
/opt/Xilinx/14.5/ISE_DS/ISE/.
   "counter" is an NCD, version 3.2, device xc3s500e, package pq208, speed -5
Opened constraints file counter.pcf.

Mon May 27 00:28:23 2013

Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "counter.bit".
Bitstream compression saved 1972928 bits.
Bitstream generation is complete.
promgen -w -p bin -o counter.bin -u 0 counter.bit
Release 14.5 - Promgen P.58f (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
0x8e84 (36484) bytes loaded up from 0x0
Using generated prom size of 64K
Writing file "counter.bin".
Writing file "counter.prm".
Writing file "counter.cfi".

#include <stdio.h>
#include <stdlib.h>

typedef int (*demo_func)();


int demo0(){ printf("Quit \n"); return 0; }

int demo1(){ printf("One demo\n"); return 0; }

int demo2(){ printf("Another demo \n"); return 0; }

int demo3(){ printf("A third demo \n"); return 0; }

int demo4(){ printf("Demo four \n"); return 0; }

int demo5(){ printf("Demo five\n"); return 0; }

int demo6(){ printf("Demo six\n"); return 0; }

int demo7(){ printf("Demo 7\n"); return 0; }

int demo8(){ printf("demo 8\n"); return 0; }

int demo9(){ printf("Last demo\n"); return 0;  }


demo_func Demos[10] = { demo0, demo1, demo2, demo3, demo4, demo5, demo6, demo7, demo8, demo9 };


int main(int argc, char **argv)
{
	int choice = -1; 

	while ( choice != 0 )
	{
	        printf(" 1 : make something \n");
		printf(" 2 : make something other \n");
		printf(" 3 : make something other than 1 and 2 \n");
		printf(" 4 : launch the fourth demo  \n");
		printf(" 5 : lanch another demo than precedents \n");
		printf(" 7 : make something v7 \n");
		printf(" 8 : make something v8 \n");
		printf(" 9 : make something v9 \n");
 
 		printf("Select the demo between 1 and 9 [0 to quit] : "); 
		scanf("%d", &choice);
		printf("\n");
		
		if ( (choice > -1 ) && (choice < 10) )
		{
			printf("return code = %d \n\n", Demos[choice]() );
		}
	}

	return 0;
}