You are on the right track, I think. Are you saying you need to do this project with a schematic rather than VHDL or Verilog? If that is the case, then you ARE going to need a 27-bit counter. The output of this counter would enable the clock input to a flip-flop, so that the output of that flip-flop changes state every two-seconds. You would then use that output to enable your display.
Does that make sense?
Barry
Yea, i dont need mux, i need demux :-D. Finally ive made it:
**broken link removed**
Now i need to do some K-maping to calculate 4 active displays, and thats it i think. :-D
I get it. The four 7-seg displays share the same 7-bit output interface from the FPGA, therefore you do have a multiplexer to define which of the four characters are sent over the 7-bit FPGA output bus.
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