[SOLVED] Spartan-3 External pinning on the FPGA

[graphene]

I now want to place the input/output signals perfectly into a particular pin as described in my circuit plan. I am using Spartan-3 XC3S400, XIlinx ISE 14.7. As shown in figures below, I need the pin 67, 65, 64 to be assigned for particular scalar ports.


However, when I use my Planahead 14.7 is shows me a layout of IO planning but doesnt specify the pin numbers but rather shows them as W22, R1, C22, etc. In the IO planning layout I have A-Y, AA, AB in column and 1-22 in row. Now how do I find the pins 67, 65, 64 ? Any suggestions?


I have my VHDL FPGA design tested. I have also set timing constraints.

 

[pbernardi]

You are using the wrong XC3S400 package. You probably want to use package TQ144 but selected FT256.

Look at this document to select the correct package: https://www.xilinx.com/support/documentation/data_sheets/ds099.pdf

 

[graphene]

@pbernardi I checkd the package it was not the wrong one. I found the answer myself. With the mouse pointers on the banks, the names of the pins in the bank lets say IO_L21N_2 can be found and that corresponds to the pin numbers.

I sincerely thank you for your reply. I also got to know some more about being cautions is packages.