shmilyzhyao
Newbie level 3
some issues about OTA
Hi,
I am a fresh research student who have an interest in "OTA design". I have read some papers concerning about OTA design and applications. And now, I am trying to design some typical OTA cells. To my disappointment, I have some troubles in simulation as below:
1. How to simulate the Gm of a fully-differential OTA?
In some papers, the Gm simulation result is given by scanning the differential input. I have no clue how to do it.
2. How to simulate or calculate the output resistance R0 of a fully-differential OTA?
3. How to simulate the open loop voltage gain of a fully-differential OTA?
I know that the open loop voltage gain of an OPAMP can be simulated by a feedback structure, in which the input offset voltage can be got automatically. OTA is a bit different from OPAMP, so is it neccesary to obtain the offset voltage before simulation? If so, how to do it?
4. How to determine the common mode input voltage?
Is it always the half of VDD? If not, how to determine it?
The problems I encountered really depressed me. Could anyone give me some help about the simulation details about them?
THX in advance.
Best Regards
Hi,
I am a fresh research student who have an interest in "OTA design". I have read some papers concerning about OTA design and applications. And now, I am trying to design some typical OTA cells. To my disappointment, I have some troubles in simulation as below:
1. How to simulate the Gm of a fully-differential OTA?
In some papers, the Gm simulation result is given by scanning the differential input. I have no clue how to do it.
2. How to simulate or calculate the output resistance R0 of a fully-differential OTA?
3. How to simulate the open loop voltage gain of a fully-differential OTA?
I know that the open loop voltage gain of an OPAMP can be simulated by a feedback structure, in which the input offset voltage can be got automatically. OTA is a bit different from OPAMP, so is it neccesary to obtain the offset voltage before simulation? If so, how to do it?
4. How to determine the common mode input voltage?
Is it always the half of VDD? If not, how to determine it?
The problems I encountered really depressed me. Could anyone give me some help about the simulation details about them?
THX in advance.
Best Regards