Solving setup violations? Why and when we use each technique

[sowmya005]

Hi friends,
Please discuss the various techniques to solve setup violations?
Please elaborate on why and when we use each technique.
How to take care of hold violation at the same time?

Thanks in advance,
Sowmya

 

[eshwartt]

Re: Solving setup violations? Why and when we use each techn

Hi,

During post-layout STA, Setup violations occur mainly due to following reasons:

1. Clock tree balancing is not done properly - In timing analysis tool we need to look for launching and capturing clock latencies, if they are not same, something is done wrong with CTS. Insist layout team to balance clk skews.

2. wen we use lower drive cells in the datapath, means cells driving huge nets and complex cells. This will increase incremental delay and add up leading to setup violations.

How to remove setup violations?

1. CT balancing must be done from layout end. If two clocks are synchronous clock balancing requirements must be met at any cost.

2. If clock tree is frozen i.e. nothing can be done from CTS end. Manually you can traceout datapath of significant violations and look for any opportunites of upsizing of cells that can reduce or remove ur setup violations. Make sure no huge incremental delay are present in datapath.

3. You can skew the clock at the capturing clock (more setup window)... Be careful while doing this you b'coz capturing flop will be launcing for next path. You should not introduce new violation by doing this.

4. If you are using multivt cells, swap HVT cells with LVT cells and SVT with LVT cells to speedup datapath ofcourse you'll lose on power for timing.

Regarding Hold violations:

1. Just add a delay buffer in datapath. Be cautious that this addition should not introduce new setup violation.

2. Use bottleneck analysis command in PT to findout common points to add a buffer to fix multiple hold violations.

2. If 1 doesn't works out skew or add delay buffer just before launch clock register Clk pin. This is also tricky stuff as 3.

Regards,
Esh....

 

[sowmya005]

Re: Solving setup violations? Why and when we use each techn

Hi Eshwar,
Thank you for the reply.
Sizing buffering cloning are the main techniques to resolve setup violations.
Keeping in mind that the delay depends on input slew and output load,
1) We do sizing when there are low drive strength cells in the path and the setup violation is because of bad input slew.
2) We do buffering when the setup violation is because of bad output load.
3) Cloning is done when buffering does not help. I dont know much about it.

Anyway we need to check the timing histogram ( to see if most of the paths are violating in the same range and the cause is same) and even the placement of the cells in the path. if there is lot of congestion, the tool might have taken detours to violate setup.

I am still not clear about how to resolve setup without impacting hold and viceversa. Please discuss about this too.

Thanks,
sowmya.

 

[eshwartt]

Re: Solving setup violations? Why and when we use each techn

Please see my comments in-line.

Hi Eshwar,
Thank you for the reply.
Sizing buffering cloning are the main techniques to resolve setup violations.
Keeping in mind that the delay depends on input slew and output load,
1) We do sizing when there are low drive strength cells in the path and the setup violation is because of bad input slew.
2) We do buffering when the setup violation is because of bad output load.
3) Cloning is done when buffering does not help. I dont know much about it.

[Eshwar]: When a cell of required drive strength is not available in the library, cascoding of cells is done to realize the cell. Pro of this method is Cascoding of cells will have reduced Cin and Cout of the resultant cell. Con of this method is if cell is complex one like AOI, routing congestion will occur at cell level in layout.
This technique is rarely used and generally tool driven...As far as I know magma layout tools does this.

Anyway we need to check the timing histogram ( to see if most of the paths are violating in the same range and the cause is same) and even the placement of the cells in the path. if there is lot of congestion, the tool might have taken detours to violate setup.
[Eshwar]: I agree, netdelay will also impact timing.

I am still not clear about how to resolve setup without impacting hold and viceversa. Please discuss about this too.
[Eshwar]: Setup and Hold are like two pans on a balance. If you do over fixing on one, other one crops up. You need to balance both of them properly through proper analysis of violating paths. There are no direct solutions for this but below fundas will help you to analyze and fix them.

There are three components that you can play with to fix setup/hold violations.

1. Clock Path or Clock Tree.
2. Datapath.
3. Constraints to drive layout tool.

1. Clock Path: If you have a setup violation speedup the launch clock path of flop or delay {Add Buffer} the capture clock path of the flop before this make sure you have sufficient positive setup slack for the next path for which this capture flop acts as a launch flop, Add buffer just before CP pin of capture clock path of the flop not anywhere in the middle of the clock path. If you have a hold violation do vice-versa.

2. Datapath: You can do all above jugglery of upsizing, buffering, cloning, VT swap, re-routing of nets to optimize datapath for setup violation. For hold, just add delay buffer of required value to remove the violation. If paths reporting for setup and hold between two registers are different analyze the paths and add a buffer after the point where both paths diverge.

3. Constraints to drive layout: We can put explicit set_max_delay -max on violating datapaths to direct the tool to concentrate and optimize on highest setup violation seen due to this constraint like below:

set_max_delay -max <some_value_lesser_than_datapath_value> -from <reg1_launch>/CLK -to <reg2_capture>/Q [For setup]

set_min_delay -min <some_value_which_will_not_give_hold_violation> -from <reg1_launch>/CLK -to <reg2_capture>/Q [For hold]

The above procedure is applicable to remap datapath intensive cells like multipliers, adders...etc. This is the way I do to optimize the violating setup paths in DC.

a. Do initial compile with constraints.
b. analyze timing results note down violating setup paths.
b. remove constraints....add set_max_delay constraints.
c. update_timing...DC sees only max_delays to optimize in its timing shell.
d. Iterate or do incremental compile.
e. repeat procedure till DC results are not consistent.

I hope same thing applies for layout also.
Any Queries please let me know...

Thanks,
sowmya.
[Eshwar]:
Regards,
Eshwar.

 

[sowmya005]

Re: Solving setup violations? Why and when we use each techn

Hi Eshwar,
Thank you for the reply.
I was just searching for info abt cloning and I found this:
Cloning is the copying of a cell, while distributing the fanouts between the original cell and its copy. It is an important way to increase the effective drive strength of a cell -by splitting its load between two copies. The advantage of this method is that it does not add levels of logic.
Buffering is another optimization technique that can greatly increase the drive strength of a cell, but adds levels of logic and thus, delay. An alternative to cloning is using parallel cells. With parallel cells, a copy of the cell is made using the same inputs. But the outputs of the cells are tied together, so they drive the load together. The advantage is that you can use this method for single fanout nets, where the load cannot easily be split. Furthermore, splitting the load in cloning often adds wire. This can also be avoided with parallel cells.

Thanks,
Sowmya

 

[eshwartt]

Re: Solving setup violations? Why and when we use each techn

Hi Sowmya,

Thanks for your reply...But iam totally confused now.....

All these days, I was under notion that cloning and parallel cells are synonyms.
Iam still not clear regarding how they are different.
Can you please point me to the docs/webpages that you've referred to.

Regards,
Eshwar.

 

[sowmya005]

Re: Solving setup violations? Why and when we use each techn

Hi Eshwar,
Please check the attachment for the document on cloning.
Thanks,
Sowmya

 

[eshwartt]

Re: Solving setup violations? Why and when we use each techn

Hi Sowmya,

I thought about this & able to visualize the differences between Cloning and Parallel cells. The basic difference between both of them is the way load distribution/sharing is done.

In Cloning, Suppose if a cell drives 4 cells, and if its drive strength is 2X, then copy the cell and connect one output of original cell to 2 cells and output of the clone to another 2 cells.

In Parallel cells, Suppose if a cell drives 4 cells, and if its drive strength is 2X, then copy the cell and connect the outputs of both of the cells (original + copy cell) together and to input pins of 4 cells. Correct me if Iam wrong.

Anyway, Thank you for sharing the document.

Regards,
Eshwar.

 

[vid31]

Hi,
I have done pre layout and post layout sta.
In pre layout, there were no setup violations.
After pre layout & CTS, I am getting large violations in the path which had positive skew in pre-layout STA.
What could be the reason for this?

Regards,
Vids31

 

[moorthy]

Vids31,
The main reason was, in Pre-layout you are using wire-load models,which contains approximate delays.
Whereas in Post-layout, actual delays from SPEF. This makes the difference.

Hope this answer your queries.

Regards,
Moorthy.S