Solving clock net DRVs in ICC2

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NeilDegruth

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Hi,
I use Synopsys IC Compiler II for the implementation and I'm getting DRC errors from the clock net such as max cap, max transition, and diff net spacing. However, incremental detailed routing or signoff DRC fixing doesn't fix anything about clock nets. How can I solve clock net DRC errors? Thank you.
 

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You can use signoff DRC tools like Synopsys IC Validator to perform thorough DRC checks and provide detailed reports on the violations.
 

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aliarifat794 said:
You can use signoff DRC tools like Synopsys IC Validator to perform thorough DRC checks and provide detailed reports on the violations.
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Yes, I can see them with IC Validator. However, as far as I remember I can't fix clock nets with signoff_fix_drc command or run CTS incrementally to fix max transition and capacitance errors. My question is how can I fix them?

ThisIsNotSam said:
Are you confusing DRC with DRV?
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I think I've heard DRV as both physical and logical DRC errors from some physical design courses and used it.

Thank you for your answers.
 

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Have you analyzed the report of the DRC violations generated by Synopsys IC Validator?
 

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aliarifat794 said:
Have you analyzed the report of the DRC violations generated by Synopsys IC Validator?
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Sorry for the late reply. Yes, I checked the DRC report by IC Validator, some of my designs have DRC violations (wrong via, route widths etc) in clock nets. If this happens on signal nets, I can reiterate route_detail or ICV fix them but what should I do on clock nets?
 

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