NeilDegruth
Newbie
Hi,
I use Synopsys IC Compiler II for the implementation and I'm getting DRC errors from the clock net such as max cap, max transition, and diff net spacing. However, incremental detailed routing or signoff DRC fixing doesn't fix anything about clock nets. How can I solve clock net DRC errors? Thank you.
I use Synopsys IC Compiler II for the implementation and I'm getting DRC errors from the clock net such as max cap, max transition, and diff net spacing. However, incremental detailed routing or signoff DRC fixing doesn't fix anything about clock nets. How can I solve clock net DRC errors? Thank you.