kumar_eee
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A CPU supports 4 interrupts- I1, I2, I3 and I4. It supports priority of interrupts. Nested interrupts are allowed if later interrupt is higher priority than previous one. During a certain period of time, we observe the following sequence of entry into and exit from the interrupt service routine:
I1-start---I2-start---I2-end---I4-start---I3-start---I3-end---I4-end---I1-end
From this sequence, what can we infer about the interrupt routines?
a). I3 > I4 > I2 > I1
b). I4 > I3 > I2 > I1
c). I2 > I1; I3 > I4 > I1
d). I2 > I1, I3 > I4 > I2 > I1
I1-start---I2-start---I2-end---I4-start---I3-start---I3-end---I4-end---I1-end
From this sequence, what can we infer about the interrupt routines?
a). I3 > I4 > I2 > I1
b). I4 > I3 > I2 > I1
c). I2 > I1; I3 > I4 > I1
d). I2 > I1, I3 > I4 > I2 > I1