sherryshe
Newbie
Hi, I got some questions.
How to deal with the backgate pin (VBGP & VBGN) settings of devices with 5 terminals while running liberate?
Q1: Is it correct to set the backgate an input pin while using define_cell command?
Q2: How to set different voltage values for backgate?
The details of my questions are below:
Q1: Liberate runs well when I set VBGP and VBGN as inputs. Besides, design compiler read the lib file (containing inverter, buffer, and gate…etc) and converted it into db format successfully. Anyway, when it comes to compile the design, an error is reported like this:
Error: The target library does not contain an inverter. An inverter is required for mapping.(OPT-101)
The partial char.tcl for characterization is below. Could you please tell me whether the settings are correct? Is it possible the error reported by design
Q2: When the 5th terminal is set as an input, the partial log is as below after running char.tcl, in which VBGP is set to 1.8v and VBGN is set to 0 by default. Could you please help me set other values for backgate pin?
And here is our lib file.
Looking forward to your reply! Thanks in advance!
How to deal with the backgate pin (VBGP & VBGN) settings of devices with 5 terminals while running liberate?
Q1: Is it correct to set the backgate an input pin while using define_cell command?
Q2: How to set different voltage values for backgate?
The details of my questions are below:
Q1: Liberate runs well when I set VBGP and VBGN as inputs. Besides, design compiler read the lib file (containing inverter, buffer, and gate…etc) and converted it into db format successfully. Anyway, when it comes to compile the design, an error is reported like this:
Error: The target library does not contain an inverter. An inverter is required for mapping.(OPT-101)
The partial char.tcl for characterization is below. Could you please tell me whether the settings are correct? Is it possible the error reported by design
Code:
compiler comes from the lib file my generating by liberate?
define_leafcell \
-type pmos_soi \
-pin_position { 0 1 2 3 4 } \
ph
define_leafcell \
-type nmos_soi \
-pin_position { 0 1 2 3 4 } \
Nh
……
if {[ALAPI_active_cell "INVD1"]} {
define_cell \
-input { I VBGN VBGP } \
-output { Z } \
-pinlist { I Z VBGN VBGP} \
-delay delay_template_3x3 \
-power power_template_3x3 \
INVD1
}Q2: When the 5th terminal is set as an input, the partial log is as below after running char.tcl, in which VBGP is set to 1.8v and VBGN is set to 0 by default. Could you please help me set other values for backgate pin?
Code:
INFO (LIB-511): (define_leafcell): Leafcell 'ph' (instance) has been identified with pin_position (0 1 2 3 4) mapped to (D G S E P).
LIBERATE parameter "extsim_exclusive" overwritten to "1" from "0"
INFO (LIB-511): (define_leafcell): Leafcell 'nh' (instance) has been identified with pin_position (0 1 2 3 4) mapped to (D G S E P).
……
Processing cell: INVD1
INFO (LIB-500): (char_library): Cannot determine VDD/VSS for port 'VBGN' in cell 'INVD1', use default values 1.800V and 0.000V.
INFO (LIB-500): (char_library): Cannot determine VDD/VSS for port 'VBGP' in cell 'INVD1', use default values 1.800V and 0.000V.
*Info* (char_library) : Cell INVD1 found in file /home/shexy/my_liberate/NETLIST/INVD1.pex.netlist
*Warning* Unable to automatically determine the related_power_pin for pin "VBGN" in cell "INVD1". Assigning to the supply referenced in the default vdd "VDD". Please check the netlist or use set_pin_vdd to avoid such warning.And here is our lib file.
Code:
cell (INVD1) {
area : 0;
cell_leakage_power : 0.00751099;
pg_pin (GND) {
pg_type : primary_ground;
voltage_name : "GND";
}
pg_pin (VDD) {
pg_type : primary_power;
voltage_name : "VDD";
}
leakage_power () {
value : 0.00764743;
when : "(I * VBGN * VBGP * !Z)";
related_pg_pin : VDD;
}
leakage_power () {
value : 0.0195762;
when : "(I * VBGN * !VBGP * !Z)";
related_pg_pin : VDD;
}
leakage_power () {
value : 0.00764743;
when : "(I * !VBGN * VBGP * !Z)";
related_pg_pin : VDD;
}
leakage_power () {
value : 0.0195762;
when : "(I * !VBGN * !VBGP * !Z)";
related_pg_pin : VDD;
}
leakage_power () {
value : 0.00195132;
when : "(!I * VBGN * VBGP * Z)";
related_pg_pin : VDD;
}
leakage_power () {
value : 0.00195132;
when : "(!I * VBGN * !VBGP * Z)";
related_pg_pin : VDD;
}
leakage_power () {
value : 0.000868983;
when : "(!I * !VBGN * VBGP * Z)";
related_pg_pin : VDD;
}
leakage_power () {
value : 0.000868983;
when : "(!I * !VBGN * !VBGP * Z)";
related_pg_pin : VDD;
}
leakage_power () {
value : 0.00751099;
related_pg_pin : VDD;
}
pin (Z) {
direction : output;
function : "!I";
power_down_function : "(!VDD) + (GND)";
related_ground_pin : GND;
related_power_pin : VDD;
max_capacitance : 0.007;
timing () {
related_pin : "I";
timing_sense : negative_unate;
timing_type : combinational;
cell_rise (delay_template_3x3) {
index_1 ("0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07");
index_2 ("0.001, 0.002, 0.003, 0.004, 0.005, 0.006, 0.007");
values ( \
…
);
}
rise_transition (delay_template_3x3) {
index_1 ("0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07");
index_2 ("0.001, 0.002, 0.003, 0.004, 0.005, 0.006, 0.007");
values ( \
…
);
}
cell_fall (delay_template_3x3) {
index_1 ("0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07");
index_2 ("0.001, 0.002, 0.003, 0.004, 0.005, 0.006, 0.007");
values ( \
…
);
}
fall_transition (delay_template_3x3) {
index_1 ("0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07");
index_2 ("0.001, 0.002, 0.003, 0.004, 0.005, 0.006, 0.007");
values ( \
…
);
}
}
internal_power () {
related_pin : "I";
related_pg_pin : VDD;
rise_power (power_template_3x3) {
index_1 ("0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07");
index_2 ("0.001, 0.002, 0.003, 0.004, 0.005, 0.006, 0.007");
values ( \
…
);
}
fall_power (power_template_3x3) {
index_1 ("0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07");
index_2 ("0.001, 0.002, 0.003, 0.004, 0.005, 0.006, 0.007");
values ( \
…
);
}
}
}
pin (I) {
direction : input;
related_ground_pin : GND;
related_power_pin : VDD;
max_transition : 0.07;
capacitance : 0.0263663;
rise_capacitance : 0.0263663;
rise_capacitance_range (0.0181643, 0.0263663);
fall_capacitance : 0.0261161;
fall_capacitance_range (0.0182719, 0.0261161);
}
pin (VBGN) {
direction : input;
related_power_pin : VDD;
capacitance : 0.000271182;
rise_capacitance : 0.000271178;
rise_capacitance_range (0.000271161, 0.000271178);
fall_capacitance : 0.000271182;
fall_capacitance_range (0.000271173, 0.000271182);
internal_power () {
related_pg_pin : VDD;
rise_power (passive_power_template_3x3) {
index_1 ("0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07");
values ( \
…
);
}
fall_power (passive_power_template_3x3) {
index_1 ("0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07");
values ( \
…
);
}
}
}
pin (VBGP) {
direction : input;
related_power_pin : VDD;
capacitance : 0.000307519;
rise_capacitance : 0.000307519;
rise_capacitance_range (0.000307478, 0.000307519);
fall_capacitance : 0.000307513;
fall_capacitance_range (0.000307457, 0.000307513);
internal_power () {
related_pg_pin : VDD;
rise_power (passive_power_template_3x3) {
index_1 ("0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07");
values ( \
…
);
}
fall_power (passive_power_template_3x3) {
index_1 ("0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07");
values ( \
…
);
}
}
}
}
}Looking forward to your reply! Thanks in advance!
Last edited by a moderator: