Softcore creation in Xilinx Design Suite

HI All

I am a final year university student. I have made my final year project using xilinx spartan-3e on nexys2 development board. I made my project using VHDL language and synthesized it succeessfully on the fpga chip. My teachers now want me to create a lab manual for my project so that future students can benefit from my project. I obviously do not want to share my VHDL code which i wrote after much difficulty. Now, I want to create a softcore for my vhdl project so that it can be implemented on any xilinx fpga in future. Just like the DCM core (which is a hardcore) i want my core to be a soft core. Whats the best possible way of creating a softcore of your own choice without any hassle.?



Please help me as i have just got a week to complete the task. :-(

I'm sorry for interfering in your thread, but if you are good with FPGA, can you tell me how to learn it?

learn this VHDL and what affordable and good tools and softwares?

thanks

Prince Vegeta said:

I'm sorry for interfering in your thread, but if you are good with FPGA, can you tell me how to learn it?

learn this VHDL and what affordable and good tools and softwares?

thanks

Click to expand...

Prince you can start up with Evita_VHDL which is a flash based application to learn VHDL , then there is a book by Pong P Chu named FPGA prototyping by VHDL examples.. have a look at that to start up with