Soft start of sepic converter does not affect gain and phase margins?

Hello,

The following sepic converter is in a car headlamp. At first it starts up and runs in stable manner. (see the simulation in LTspice) . However, there is then a Load Dump occurrence, involving the input voltage to the converter going up to 20V, then coming back down to 12V again.

The sepic converter resumes operation, but this time it becomes totally unstable.
Why is this?

With the emitter of Q4 connected to the “Ith” pin of the PWM controller, the converter gets restarted with a “soft-start”, and then the restart of the sepic converter is perfectly stable.

Why is this?…..i didn’t think whether or not a converter was restarted with a soft start had any effect on the gain and phase margins?

The schematic and LTspice simulation are as below.

How do you know that the phase margin is sufficient under all possible operation conditions. The circuit is nonlinear, e.g due to the LED I/V characteristic or possible saturation of the error amplifier, so there are many ways to achieve dynamical instability.

You have to run the simulation above with the Q4 emitter connection to "Ith" broken in order to see what I am talking about.

The Q4 connection stabilises it.

when you break that connection and run it, you see it first start up in perfectly stable operation, then the second time it starts up, after the load dump, it is totally unstable....I cant understand this.

...the solution comes by reconnecting Q4 emitter, but Q4 only operates during start up, so howcome connecting Q4 makes it stable during steady state operation

As I say, you have to break the connection between q4 emitter and "ith" pin to see what I am talking about.

I'm not quite sure I understand. In your file the collector of Q4 connects to Ith, emitter is at ground. That circuit seems to implement a soft start as intended, and when I disconnect the collector from Ith the soft start is gone but the response to the 50V line transient doesn't really change significantly. And there's no real "restart" in this circuit once it initially powers up, that I can see anyways.

Also from inspection it looks like even at 12V in, the stability margins aren't very good to begin with....

OK, thanks for looking into it, if you wish to run the below LTspice simulation for 30ms, the question is, why is it beautifully stable from 6 to 12ms, and then horrendously unstable from 18ms onwards?

I thought that I already explained the problem in post #2. The circuit obviously isn't stable in large signal behaviour. Once you manage to excitate a sufficient large deviation from steady state, the error amplifier exceeds it's linear range and the circuit falls into a kind of relaxation oscillations.

The initial startup has different initial conditions and increases the duty cycle slowly, but the restart doesn't without additional means.

Ok I see it now. For some reason when loading your file U3 was left out and the load dump circuitry didn't function because of it.

I agree with FvM, the oscillation is due to very nonlinear behavior, so it will only arise under large transient conditions, which is why the soft start circuitry helps eliminate it. If it were me I would attempt to mitigate the behavior by changing the control loop, and then add the soft start as added protection.

OK thanks, I will do that, of course, as I mentioned, ifind these transconductance error amp pwm controllers make the control more difficult.
I appreciate that I will take your advice and calculate it out.