SOC synthesis with paths failing

In a SOC synthesis if it is found that some paths are showing timing violation, what should we do for those paths then? What are the relavant design compiler commands.

Just look at the critical path which it is reporting and analyze why it is failing. There could be several reasons for its failure. If it is a setup violation, The number of levels of combo-logic might be higher in your critical path. There could be wrong constraining i.e. some times a mutli-cycle path is not constrained and it is analyzed for a single clock cycle, It will show errors.
There could be clock skew issues in your clock tree as well for the timing violations. This is just a glimpse of the big list and there are several techniques to overcome timing viloations.

I dont have any document describing all the techniques.

Before looking at the commands in design compiler, list down what you wanted to do to your design.

Once you have them, Just post your requirement here.

What are optimization contraints for doing synthesis by design compiler? To me timing constraints like create_clock, set_input_delay and set_output_delay, set_max_area are optimizing onstraints. Is there any other optimizing constraints?

dcreaddy1980

If many paths are found to fail for a SOC, what else do you do? Do you run synthesis particularly for those set of paths? What are the command for this. I was asked this question from somebody else that "If many paths are found to fail for a SOC, what else do you do?" The other person was not happy with my answers that u provided in #2.

"compile -map_effort {low|medium|high}" is one good command in DC which will allow the tool to perform optimization. When you use this command, It doesnt get gurantee that all the critical paths will go off and you will have timing clean design.

"set_flatten true -effort {low|high|medium}" command will also does optimization.

one more command would be : "ungroup -flatten -all" This will remove your hierarchy and you will get a flattened netlist.

Place set_dont_touch_network on the clock and reset network so that DC will not buffer up the network.

dcreaddy1980

I told many of what you wrote in post no. 4 to that person who asked me "If many paths are found to fail for a SOC, what else do you do?" He agreed with these , but he was expecting something else other than this. He was providing hints like : group_path ......, some conatraint command. Do u have any idea on this?

Regards

Hi ASIC_int,

group_path is effective as you can separate R-R paths from I-r,R-I and I-O paths...If you do not separately group these and you have a worst path as I-O path the tool does not optimise the other remaining violating paths as it aims to reduce WNS rather than TNS..so even when there is a possibility of optimising the more important R-R path it will not do so as you haven't explicitly guided the tool...So now when you group paths you can optimise paths along each of the four timing paths thus reducing the no of violating paths and TNS as well..

cheers,
Pavan GS

pheni

Please let me know the full form of WNS and TNS?

Regards

Worst Negative Slack(WNS) This is the slack of most critical path in the design. It's value can be negative, zero or positive. Negative value means there are timing violations in the design. Zero or positive means there is no timing violations.
Total Negative Slack(TNS) is the sum of all the negative slacks in the design. If WNS is zero or positive. It's value will be zero.

Hi phoenixpavan

What are u suggesting then? Are you saying the folowing:

1. Group the four paths.
2. Compile then with map effort medium.

Do you want to mean that if the paths are grouped in four categories the tool will spend time in optimizing the three group of paths equally irrespective of where the critical path is there?

Do we need to do something after grouping the paths , so that design comiler optimizes
the three group of paths equally irrespective of where the critical path is there? What changes are necessary for the above and what options in compile command should be switched on there?

Regards
Regards

Hi Asic,

yes, that is what I meant,

for the way to do it you can just refer a tool ug..and you should be done with it.

cheers,

Hi phoenixpavan

I found the design compiler ug. It provides a general description of synthesis. It does not write what you are stating here to group the path and then compile.

I think what you want us to do is only to group the four catagories of path before the compilation. That is you mean to group the four path and after that write the compile command with all its usual options like - map effort etc. in the synthesis script. Is it?

Regards

Hi ASIC_int,

group_path -name inputs/outputs/combo -from/to [all_inputs]/[all_outputs]

the R-R path is in clock path by default so this way you can divide it inputs/outputs/combo/clock so that each path group gets optimised independently and one Worst violator in one group do not block the optimisation of another violator in another group

cheers