SOC design for MPEG IC - reducing pin count

soc count

we are developing an mpeg-2 decoder chip with two TS SPI/one IDE/one uart/one ethernet RMII interface/two smart card interface/16 bit flash/32bit sdram interface/pcm &spdif audio interface/3 way video DAC analog out / CEIR /two I2c /CSPI(connect to VFD ctrl IC on board) /GPIO and VCXO、JTAG ,chip mode ctrl and ATPG test pins etc.

we expect to use a 256pin QFP package. but there are something hard to do it. For there are many additional ground and power pins needs, the amount nearly about 1/3~1/4 of the useful functional pin.

so we are thinking about how to reduce the functional pin of the chip. a way is to share it between two interface. like IDE share data pins with Flash. the other way is to reduce the additional ground and power pin.


I'm wonder how the smart*MPEG can be put into 208pin package.

anyone who can give some sugections to help us to go to the correct direction to solve the problem. it's welcome.

thanks

how to count connect ic

Roli, this would be a good time for some advice form you, IC layout not my strong point :?

Do you need 2 smart card interfaces to be accessed at same time?

If NO then you could use a dual inteface ISO7816 interface IC from Philips and that way you only need

SC_DAT Data I/O
SC_CLK Clock
SC_RST Reset
SC_VPP VPP control signal
SC_VCC VCC Control Signal
SC_EN Smart card inserted signal
SC_SEL IC card select A or B

# 7 pins, Tot 7

this should also need one GND pin, but you should only need a few mA if you use a physical IC for ICC interface as it will supply the max 200mA needed for the card.

# 1 pin, Tot 8

For a IDE enabled solution you would really need a 32 bit wide interface for the host transfers and have the control liones hard coded.

The same data bus can be used, for hsot address AND data if you add the contol signals in to do it. So say 32 pins plus 4 pwr & 4 GND per 8 bit PIO array plus 10 control lines for buffers, IDE, DMA and so on.

# 32
# 4
# 4
# 10, Tot 58

2 x TS interfaces so you need 1 x Valid, 1 x clock, 1 x pkt start, 1 x stream error and 8 data bits per SPI. 4 GND & 2 PWR

# 12
# 12
# 4
# 4, Tot 88

2 x I2C

# 4, tot 92

1 x UART, RX, TX only plus 2 PWR

# 4, Tot 96

1 x JTAG, plus PWR

# 9, 105

Front panel interface and keypad (4x4) multiplex with display, plus PWR
20 pins plus 4 PWR

# 24, Tot 129

Audio out, 9 pins including BCLK/ACLK/LRCLK/PCM/SPDIF/SPDIF/PWR

# 9, Tot 138

Analog DENC out, Iref, Vref, VCC, DAC outs plus PWR

# 10, Tot 148

VCXO, pwm output, clock in plus PWR

# 4, Tot 152

More later, but even with the interface for the ethernet PHY you have plenty pins left in you package budget.

If you look above you have assumed you need to have 32 bit data and address bus (32 plus 28 address lines) but if you use external glue logic you can share the 32 bits as Address/data like PCI bus.

Hope some ideas are useful to you

reduce pin count

Any body know where i can buy Fujitsu SmartMpeg SDK ?

how do you count the pins of a ic

jhonny_yang said:

Any body know where i can buy Fujitsu SmartMpeg SDK ?

Click to expand...

Do not cross post same question across different forums or topics.

Is enough to ask once :wink:

mpeg ic

I am not clear why you need two I2C bus. I2C bus can be used to connect more than one devices via only two pins SDA and SCL.

if you connect the I2C bus to a demodulator, link IC, demodulator, RF synthesiser or other device it can be better to be able to turn off the bus when not used.

Also if you have different speed devices they can connect to seperate bus, or have on int driven and the other polling.

Cannot do anything if you only have one

easetv wrote:
I am not clear why you need two I2C bus. I2C bus can be used to connect more than one devices via only two pins SDA and SCL.

-> I think the I2C bus is an important extension bus for DVB device.
You may necessary to control E2PROM, RF tuner/demodulator ,Audio DAC, Frontpanel microcontroller through I2C bus.
two I2C bus can provide more driving capacity. and also facilitate the layout of 2 layer PCB.

Ha, I know the most simple way to efficient reduce the pin count is pin sharing. Smart*MPEG even sharing pin between four kinds function point.
that is to say, many functions of Smart*MPEG can't be used at same time.

And to reduce the additional ground and power pin is hard and need technology and experience.