SoC based on 51core problem?

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davyzhu

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Hello all,

I'd like to design a SoC based on 51 core, and I have to add several SFR flags due to the design(for example: SFR_1 ... ), the SFR should be accessed by the assembly language like MOV SFR_1, #00H,
shall I change the 51 softcore(it is based on Verilog), or can I realize it by writing assembly language.

Regards,

Davy Zhu
 

It depends on how these new SFR should be mapped. If they can be placed in usual DATA area, then just use EQU directive to define their names. Also, if they are just a flags (with 0 and 1 states only), you can map them into the BIT memory area.

But, if you want these new SFR to be directly available by external hardware, then you have to map them into XDATA area and use indirect adressing with DPTR or to change Verilog code to map any internal DATA location to external I/O.

Ace-X.
 

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