Snubbers for 3-level T-type 3-phase inverter

You don't really need a lot of snubbing - last time you did because your control circuits were quite susceptible.

always a good idea to control the turn on speed

if you are going to use snubbers the R & C should be right across the D-S - not as drawn.

There should be low inductance DC-link capacitors for the center node. RC snubbers shouldn't be required if you manage to keep inductance of commutating loops low enough.

Also if there is any braking of the motor load - or other type of reverse power flow - you'll need LARGE braking resistors and IGBT's across the bus.

The IC talks about adaptive deadtime during startup only and the RC values for controlling DT are single ended were only tau= 1ns. Also the FETs may be rated for 800V. All of which explains why you don’t want to add snubbing losses but may need to shield.

Remember - losses in any snubber R are up to C.V^2 Freq

so for 800V, 2n2 and 30kHz - you will get 42.24 watts

if the GD timing is such that you can limit turn off volts to 400, and ditto for turn on then this becomes 10.56 watts - still quite high

perhaps, 1n0 is a better starting point ?!

Easy peasy said:

Remember - losses in any snubber R are up to C.V^2 Freq

so for 800V, 2n2 and 30kHz - you will get 42.24 watts

if the GD timing is such that you can limit turn off volts to 400, and ditto for turn on then this becomes 10.56 watts - still quite high

perhaps, 1n0 is a better starting point ?!

Click to expand...

your power formula is incorrect and must include R , Rdson,

D.A.(Tony)Stewart said:

your power formula is incorrect and must include R , Rdson,

Click to expand...

Respectfully - your comment is non sequitur - try reading again, and remember Rsnub >> Ron, so Ron is quite immaterial

as to the other - the maths and the practical side bear out the equation, where R is sized any where near optimally, e.g. R ~= SQRT ( L/ C )

Practically and logically, when R = infinity there are no losses in R, and for R = zero, peak currents are limited by external factors - so power is almost zero ( for a piece of copper wire ) - but in between the equation holds well.

What does affect snubber losses is speed of turn on of a device and of course turn off.

Just from physics 101; any step change provided to an RC circuit, the losses in the R are 0.5 C. V^2, regardless of the value of R or C, as long as the step lasts for ~ 5x the RC time constant

similarly for discharge, hence C. V^2 F for power in the R, QED.

In the limit for a perfect system ( volt source drive ), the peak current tends to infinity as R tends to zero ( also small time constant ) so the power loss in 0.001 ohms is still given by the expression ( as the peak current is very large - perfect system ) - The maths also predicts the loss of power to RF radiation when you put two caps together of unequal voltage - again due to the high peak current ( and fast rise time ) - assuming very low L, and low R.

Hi,

when one has an RC ... and one charges the capacitor to a fixed voltage Ve, then
* the energy stored in the capacitor is 0.5 x C x Ve x Ve
* the identical energy is dissipated in the resistor ... interestingly independent of resistor value. The resistor just determines the timing.
* when the capacitor is discharged via the same resistor .. then all the stored energy is again dissipated by the resistor. so, again: 0.5 x C x Ve x Ve

So when one drives (push-pull) square wave into an RC the dissipated power is: in face C x Ve x Ve x f ... independent of the resistor value.

For sure this is only true when the source is ideal and the frequency is low enough to fully charge/discharge the capacitor (error within tolerances) and no other losses are involved.

Klaus

Easy peasy said:

Respectfully - your comment is non sequitur - try reading again, and remember Rsnub >> Ron, so Ron is quite immaterial

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Thanks for your explanation.

Wolfspeed's SiC FET array with 25kW 3ph design specify a nominal DT=300 ns while Coss = 209 pF and RdsOn=21mΩ @ 25'C


I don't know what his active PFC bus DC voltage is.

Can you estimate the transition times. (2 per cycle) with / without the proposed snubber?
Since these FETs are rated for 1200V, unless there is no load, snubbers may not be needed to protect the FETs and may not reduce the slew rate much for EMI purposes.

I would be inclined to duplicate Wolfspeed's design without any mods with full BOM and Gerbers.

There is a time when RdsOn is higher than R.snub and that is during FET Toff/Ton when the snubber is used so snubber Pmax will be slightly less than CV^2/2.

There is another time when the R.load is greater than R.snub depending on R.load=V2/6Pmax ( for half of 3 phase FETs). = 75 ohms (min) for 25 kW @ 800Vdc.

Thus Pd of the snubber R will vanish for turn-off at low load currents.

e.g. assuming 800V²/25kW = 25 Ω or 75 Ω/phase when R.load = R.snub, the snubber has reduced 50% only during Toff.

The output LCL filter seems compact and effective at 50 kHz for EMI attenuation.
There may be resonant ringing in FET transitions, but how low is √(L/C) = R.snub

Maybe the RC.snubbers are ineffective for these design values.

D.A.(Tony)Stewart said:

Thus Pd of the snubber R will vanish for turn-off at low load currents.

Click to expand...

This is not quite the case - the dv/dt on a switching node is heavily dependent on dead time and turn on speed of the next device ( turn off is usually designed to be fast in an inverter to lower losses ) - and load.

As long as the volts commute from one rail to the other at - or faster - than the RC time constant of the snubber - there will be noticeable losses in the snubber R. ( and of course they commute even at zero to no load due to the const freq sw action of the devices in an inverter )

This can be generalised to : " Any AC across the snubber will heat the snubber resistor "

Your other comments have already been covered in the above. For example if the Ton and or Toff are less than 100nS say, this is a small part of the snubber RC time constant and thus can be ignored for snubber power calcs.

It should be remembered that the classic RC snubber is really rather more of a turn off snubber than anything else,
at turn on the device must discharge the C thru the R, adding a current spike to the device at turn on ( and therefore extra device losses ).

I think there is a contradiction.
If Ton and Toff are less than the RC time constant, the cap will conduct current and R may dissipate equally for SiC. This is type-T PWM so it dissipates more on the Ton for the 2 reasons I stated. I agree Toff is the target for classic flybacks or large ESL when there is ringing with a light load.

But as I said before a light load and RdsOff do play a roll in decreasing Pd on R.snub during the turn-off.

I tried a simple half-phase sim modelling the Wolfspeed FETs and Toff spike decreases with load current, but Ton spike increases and the total 2f peak power changes much less with load.

It seems an active clamp may be needed with the LCL filter to load.

I think Easy Peasy is correct.

In a series RC circuit which switches between two voltages (V1 and V2), average power dissipation in the resistor is P = f*C*(V1^2 - V2^2). This is true so long as the circuit ends up at a steady state every time it switches (i.e. the switching period is much longer than RC) and the rise/fall time of the applied voltage is much faster than RC. As long as those conditions are met, the resistance of the FET/snubber doesn't really affect dissipation in the snubber.

Is there a way to determine the RC snubber values before building the circuit? In any paper I read (including the one in the attachment, page 12), it needs measurement of the ringing frequency to get the DC bus inducance, and from there calculate resistance.

The only resistors for 1,000 Vdc (or 500 Vdc DC bus rail to mid-point) are TO-220 type; they also have a power rating > 10 W, so I should be okay in terms of disipated power.
For capacitor, the paper assumes C_snub = [1/2 ... 2] C_oss Output Capacitance. For C3M0075120D, C_oss is 58 pF. For now, I was thinking of provisionally adding pads to the PCB and then mounting later if required.

Pavg = f*C*(V1² - V2²) I agree, that is true as Tau and duty factor controlled by R cancels out for Pavg.= Ppulse * d.f.

My point, when the FET turns off faster than the RC =tau during dead-time the loop current is supplied from the load filter which may have higher series resistance than Rsnub when RdsOn is OFF and thus may diminish Psnub.

If you use the integrated SiC FETs the parasitic ESL should be less than 10 nH and with DC busses it is possible to make much larger common mode ESL so together with low ESL caps and a minimal loop layout, no snubbers should be needed. This is a big advantage for 25+ kW inverters.

D.A.(Tony)Stewart said:

My point, when the FET turns off faster than the RC =tau during dead-time the loop current is supplied from the load filter which may have higher series resistance than Rsnub when RdsOn is OFF and thus may diminish Psnub.

Click to expand...

you are perhaps overlooking that the other device has to turn on sooner or later - the dv/dt caused by this causes snubber dissipation.

If the load filter is a current source ( inductor ) during dead time - it causes a dv/dt across the snubbers - it's resistance would have to be very high indeed to reduce snubber dissipation. As we are talking about a power inverter - any filter L resistance will be very low ( << Rsnub ) and therefore immaterial to the snubber.

It appears the essentials are being overlooked by some, i.e. if the voltage commutes from rail to rail - inside the RC time constant - the snubber power will be noticeable. For a T type inverter ( bad label, really should be just said as 3 level ) at turn off of the bottom device the mid point can rise all the way to the +ve rail, before the mid rail devices turn on - pulling the midpoint back to half rail - so snubber losses can easily be higher than C.V^2.F for a good deal of each AC output half cycle.

For the OP, snubber R's in series are fine for volt withstand, and to give total power, make sure the snubber caps are well overated for the task ! series & parallel if you have to.

Snubbers are not in fact used in many commercial designs - where the control can handle the RFI produced.

--- Updated Oct 12, 2024 ---

mike buba said:

Is there a way to determine the RC snubber values before building the circuit?

Click to expand...

The paper you refer to is based on mouse power electronics - since your requirements are for using snubbing to reduce noise to a low enough level that your control will work - there is no easy way to know enough before hand to calc snubber values.

At 30kHz, you have to start with sensible values that will not produce excessive heat in the snubber R's, nor cause excessive heat in the power devices,

controlling turn on speed is the bigger lever here to reduce RFI noise produced.

A general rule of thumb is to have the dv/dt >= 100nS for rail to rail excursions, for low RFI, so if a turn off current is 10A, and the rail is 800V - the capacitance must be 1.25nF total. If we go a little past this and put 1nF on each device - the associated R will see at least 20W @ 30kHz ( 470pF = 10 watt )

[ N.B. if you can keep the V excursions to 400V this will be 4.8 watts ( and 2.4 watts for the 470 pF ) ]

How to calc the R ? - ideally we need to know the circuit stray L ( Rsnub = ~ sqrt ( L/ Csnub ) ) so say the wiring L = 200nH, Rsnub = 15 ohms.

There is another rule too, if the turn off current is say 10A peak, and we want to see say half rail at turn off across the device, so 400V / 10 = 40 ohms to achieve this.

So we can see straight away where the ball park value will lie,

N.B. higher pcb and wiring L requires larger R, and in fact larger C to soak up the energy in this stray inductance - so design for least L.

mike buba said:

Is there a way to determine the RC snubber values before building the circuit?

Click to expand...

You can estimate the snubber capacitance somewhat, but the resistance depends directly on parasitic inductance so it's a guess at best. You should expect some iteration to be necessary.

mike buba said:

The only resistors for 1,000 Vdc (or 500 Vdc DC bus rail to mid-point) are TO-220 type; they also have a power rating > 10 W, so I should be okay in terms of disipated power.
For capacitor, the paper assumes C_snub = [1/2 ... 2] C_oss Output Capacitance. For C3M0075120D, C_oss is 58 pF. For now, I was thinking of provisionally adding pads to the PCB and then mounting later if required.

Click to expand...

For an RC snubber to be effective, its ESL has to be much lower than the ESL of the circuit being snubbed. So TO-220 resistors should be avoided unless you absolutely need them to handle the dissipated power.

So long as your layout is decent and you control the rise/fall times with appropriate gate drive, you shouldn't need 2.2nF of capacitance for each FET, probably more like 500pF. In that case you should be able to make due with a small array of surface mount snubber resistors (make sure they are rated for pulse operation). By using a series/parallel array of resistors you can also avoid needing special high voltage resistors.

Wow - it's like some one read my post and then re-phrased it.

Wow . Looks like Wolfspeed agrees with me.