Smartmodel question regarding design using xinlinx isev4

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zhoury

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Smartmodel question

Does anyone have experience in simulate using smartmodel and design using xinlinx isev4. I want to construct a board level simulator enviroment using these two tools. I need using smartmodel's 386 model and fpga designed using xinlinx. How can i do this?
 

i never used it but from what i read time ago in synopsys docs, you have to
put together in a suitable simulation environment the 386 BFM
(Bus Functional Model) and the Xilinx VHDL code. Then you write
some simulation cycles for the 386 and let the simulation engine
execute it and watch how your FPGA react.
 

Who know how to get USB bus Smart model simulation code?
I need use a testbench to simulate USB design. Please help me!!!
Thanks in advance!
 

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