Small issue in MOStransistor saturation criterion

Hi all,
For transistor to be in saturation which should be met or both should be met
1. Vds>Vdsat
2. Vds>Vgs-Vth
Kindly see the simulation result below of HSPICE . w/l is 10/0.4
Vdd is 1V and VDs is 30mV

element 0:m1
region Saturati
id -1.2094u
ibs 2.957e-20
ibd 5.5275f
vgs -550.0000m
vds -30.0000m
vbs 0.
vth -540.9739m
vdsat -78.9677m
beta 1.2436m
gam eff 516.9256m
gm 16.6472u
gds 30.5579u
gmb 4.7986u

I hav seen the same thing happenning in cadance..so there is nothing wrong with the tool..the basic issue is with the models..I doubt that vdsat=k1+k2(vgs-vt) for the BSIM3..

u just take care of following..
1. vgs shd never go below vt..there shd be a margin of 30-40mv..in 0.13 u can go upto 20mv vgs-vt..
2. vds > vgs-vt..it will be a good idea to make it vds>1.5(vgs-vt)

regards

Dear opamp741,
I am trying to simulate a simple PMOS current mirror. the structure is diode PMOS load and a current sink connect b/w drain and gnd.
I need to have Von as low as 30mv for a current of as low as 0.5uA.
the w/l calculated from 1st order equation when plugged in cause the MOS to go to cutoff.
For Kp of 46 w/l=24 (w=9.66u and l=0.4u)
The hspice simulation result are follows
subckt
element 0:m1
model 012
region Cutoff
id -499.9991n
ibs 1.225e-20
ibd 7.7646f
vgs -465.8752m
vds -465.8752m
vbs 0.
vth -540.4868m
vdsat -53.4456m
beta 1.2015m
gam eff 516.9929m
gm 9.8224u
gds 77.3077n
gmb 2.7959u

The following are for w=26u and l=1u
subckt
element 0:m1
model 018
region Cutoff
id -499.9990n
ibs 1.186e-20
ibd 18.6828f
vgs -465.2262m
vds -465.2262m
vbs 0.
vth -533.8077m
vdsat -54.2220m
beta 1.1275m
gam eff 576.0587m
gm 9.6217u
gds 22.0535n
gmb 3.0538u

Here I have the problem, to get the MOS in saturation. only 2 option exsist
1. Increase current or decrease W/L. Both of them would lead to vdsat increase.
How do we get out of this problem.

step 1 and 2 are same. i mean vsat = vgs-vt. so for the transistor to be in saturation vds > vgs-vt i.e, vds > vdsat

hi, ambreesh
you should be careful when your Vgs is close to Vth.
The transistor may be in weak or moderate inversion instead of strong inversion.
here is a paper about that,
regards

Dear ppenday,
Kindly look at the simulation results, the design for Von of 30mV but could not have vdsat that low.