Small doubt regarding verilog

[rknmahesh]

I want to design a base band of a system using verilog. It should work at very low power. Whatever I do in verilog how to ensure that it should have lowest power. Or shall I do basic elements in transistor level to ensure that they have low power.

Thanks in advance

 

[dftrtl]

You need have architecture to implement with less number of registers. Like some logic can be working at high speed and little logic at Half the frequency

 

[rknmahesh]

But as if in the individual blocks can we decrease the power b'coz i need my design to be an ultra-low power design

 

[dftrtl]

You divide you individual blocks to further low frequency to save power

 

[skn.1357]

Hi,
For ensuring low power consumption you should follow these design rules:
1. use high threshold device (Hi-VT) so that leakage can be minimized,
2. by modifying the logic structure such that the toggling rate of transistors can be minimized,
3. use gated clocks, so that idle portions of your design can be turned off,
4. lower the clock speed.

 

[sina.parsnejad]

All said above are correct
beside them, you can always use the core elements
I think there are elements there that can be used for low power purposes

 

[skn.1357]

Hi sina.parsnejad,
what do you mean by "low power elements"? I think it's the high Vt transistors, isn't it?