Phytex
Member level 4
opening vslick from modelsim
Hi,
my company have bought Visual SlickEdit 8.01 (details see at h**p://www.slickedit.com). This programming editor works really very well (greate tool), but I have some problems to implement ModelSim as compiler for Verilog / VHDL. Can somebody give me a tutorial what I have to do to implement ModelSim in SlickEdit.
Will be nice if I can double click on a error and the courser jumps to the error!!
THX for help. -Phytex
-- Please no postings of warezz in this Threat!!!!
Hi,
my company have bought Visual SlickEdit 8.01 (details see at h**p://www.slickedit.com). This programming editor works really very well (greate tool), but I have some problems to implement ModelSim as compiler for Verilog / VHDL. Can somebody give me a tutorial what I have to do to implement ModelSim in SlickEdit.
Will be nice if I can double click on a error and the courser jumps to the error!!
THX for help. -Phytex
-- Please no postings of warezz in this Threat!!!!