slack paths, reduce it in design

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Dear all;

How to reduce the slack paths in design, what is the logic of thinking to reduce it.

Thanks in advance.


do u mean slack?
it is of two types.....positive or negative.

suppose, setup slack is positive.means in your design there is no violation.if slack is negative, there is some violation.
 

can u pls elaborate in detail......!
 

can u pls elaborate in detail......!

setup slack = Required time - arrival time

if slack is positive then required time is more than arrival time. so, data may be stable before active edge of clock. thus violation is reduced.
 
I believed you mean how to reduce the negative slack, I means reduce the combinational logic between two memories element (flip flop).
Added pipeline is a solution.
 

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