skew for common clock path

chevuturi said:

do we have skew for common clock path ? if no why ? if yes how do we calculate ?

Click to expand...

No, because it is same physical line so it can't have skew with itself.

kaz1 said:

No, because it is same physical line so it can't have skew with itself.

Click to expand...

You won't get a job at AMD with that answer.

skew as in clock skew from clock tree implementation: no.
you may have jitter from one clock edge to the next, which is sometimes also accounted under the term "skew".

D.A.(Tony)Stewart said:

You won't get a job at AMD with that answer.

AMD Technical Information Portal

docs.xilinx.com

Click to expand...

The post is NOT about clock skew but common clock path (CCP) skew. The dashed line below:

Could you please more elaborate with this picture ?

ThisIsNotSam said:

skew as in clock skew from clock tree implementation: no.
you may have jitter from one clock edge to the next, which is sometimes also accounted under the term "skew".

Click to expand...

why Professor ? why skew will not be included in common clock path ?

chevuturi said:

Could you please more elaborate with this picture ?

Click to expand...

Delay occurs in any path be it clock or data. Skew term is used to indicate delay difference between multiple paths such as clock paths or data bits path. Clock path from clock pin to launch register will have skew relative to clock path from clock pin to capture register.

The section of clock path that is shared as in the above picture is the common clock path(CCP). Of course it suffers delay but this delay is same to either register.

The term common clock path is primarily related to CCPR removal (common clock pessimism removal) and that is what I assumed your question was centered on. Clock Pessimism removal = common clock max delay - common clock min delay
It is added to capture register clock path for setup calculation, but subtracted for hold calculation.

Jitter rises with buffering to minimize skew from latency so keep your insertion delay to a minimum.


XOR gates add unequal path latency due to the internal logic, which reduces margin to clocking errors at very high speeds.


Upstream device delay and board trace delay need to be specified
► Maximum delay for setup analysis: set_input_delay -max
► Minimum delay for hold analysis: set_input_delay -min
► Referenced to the launch clock edge

chevuturi said:

why Professor ? why skew will not be included in common clock path ?

Click to expand...

the post from kaz1 explains why. skew is a difference of two delays. if the path is the same, the difference is zero. therefore, no skew.

ThisIsNotSam said:

the post from kaz1 explains why. skew is a difference of two delays. if the path is the same, the difference is zero. therefore, no skew.

Click to expand...

That was a fuzzy cloud answer. Reality is different.

Yes, skew can exist in a common clock path.

Clock skew refers to the variation in the time at which a clock signal reaches different components in a system. Ideally, in synchronous digital systems, we want the clock signal to arrive at all components at the same exact time. However, due to various factors such as differences in trace lengths, loading, signal integrity issues, temperature variations, and manufacturing variations, the clock signal may arrive at different times at different components. This difference in arrival time is known as clock skew.

The result can be a metastable or race condition if the setup or hold conditions are not met. Before automated analysis systems existed, we had to do a path analysis with datasheet worst case timing over the environmental temperature range. CMOS rise times and prop delay thru gates increases with temperature since load capacitance tends to be constant while RdsOn = Vol(max) / Io increases with temp. Industry standard small scale integration parts varied between manufacturers for nominal and best case values because of lithography improvements or the design of RdsOn was lower producing faster risetimes. RdsOn increases with lower Vdd which is another variable yet the tolerance for RdsOn can be 25%, 33% or 50% depending on the logic family, supplier and vintage of the part design. The voltage specs for Vdd max, will have lower the RdsOn to reduce risetime, but industry standards for common parts tend to be the same but hard to find, so when comparing second source parts, compare these parameters Vol/Io vs Vdd @ x pF, Vdd with risetime.

You will learn how to calculate them when you understand how trace impedance is calculated for Zo^2=L/C and rise time related to sqrt (L*C) depending of the measurement parameter 0 to 50%, 0 to 64%, 10 to 90% or whatever. Trace effective series inductance (ESL) or simply L is a logarithmic property that depends on l/w dimension ratios are typically 0.7 nH/mm +/-50% and capacitance 0.3 pF/mm nominal increases with ground plane gap reduction, Dk or co-planar gaps. (Saturn PCB design a good free tool to see this) Using FPGA tools to compute margins for various clock speeds vs temp & Vdd tolerance does this for both "launch and capture" or Tx & Rx but it is good to at least compute all the variables manually to appreciate the complexity when doing a hundred different paths with a common clock as we had to do before you had smart tools. Rise times also increase with fanout and is only limited by the effect of cumulative load capacitance and desired timing margin. or clock skew with jitter, rise time and delays combine with input threshold variations up to +/-50%

p.s.
You don't have to worry much about trace delays if the risetime is greater meaning the linear or spectral content or significant harmonics are any lower than 10% of the wavelength. BW (-3dB) = 0.35 / Tr (10 to 90%) and 3rd harmonics are almost 10 dB down from the fundamental sine.

Sorry, your answer is borderline off topic. You are talking about PCB design, while OP clearly is talking about CPPR.

My experience may be a bit earlier than yours, so your comment seems a bit metastable. The OP was not as specific as the answers.


Do you think my comments are not relevant for 3GHz ASICs?

No digital tool doing CTS has any notion of backplane, or wavelength, or trace delays.

You are mixing skew (as digital designers call it) with jitter.

Can you explain how the CCP skew is affected by fanout capacitance and input threshold of each device??

Yet all digital circuits are inherently analog.

FWIW This may be of some benefit to others.


FYI Jitter is just the short-term deviation from ideal position in repetitive time intervals.

Jitter gets amplified by variations in thresholds in a clock tree buffers with added fanout capacitance, and with ps delays by ground capacitance, which is why insertion delays should be minimized.

kaz1 said:

The post is NOT about clock skew but common clock path (CCP) skew. The dashed line below:

View attachment 187854

Click to expand...

Does this contradict your assumption that CCP has no skew?

CCP is not affected by variations in fanout cap or driving strength or input threshold. There is another thread where this topic is being discussed and I mention crosstalk there. Crosstalk does matter because it is not constant from one edge to the next.

Yes, yada yada, all digital circuits are analog, but they are analyzed as digital circuits by the digital CTS tools that handle CPPR.

ThisIsNotSam said:

No digital tool doing CTS has any notion of backplane, or wavelength, or trace delays.

You are mixing skew (as digital designers call it) with jitter.

Click to expand...

these tools are useful for most common IC designs, but I don';t think you'd get a job at AMD if you said the common clock has zero skew.
That is only true for the ideal common clock. One must choose differential mode clocks with very high symmetry and balanced RdsOn and then determine the tolerance on Capture thresholds.

Remember that clock skew is the quasi-static variation between launch and capture. But the clock does not determine the threshold that data will be captured and these thresholds do have a wide tolerance in batches and yet smaller variation of identical designed loads within the same device. But they are not ideal and this understanding might be necessary to design a 32 core 6 GHz CPU at AMD with 3 nm lithography.

Do you still stand by your comments? I do. or please correct me where I was not accurate. Disregard the ancient use of common clock to backplanes but the rules still applied back then. In the Cray 1, they used radial star distribution patterns to distribute clocks.

D.A.(Tony)Stewart said:

Can you explain how the CCP skew is affected by fanout capacitance and input threshold of each device??

Yet all digital circuits are inherently analog.

--- Updated Jan 14, 2024 ---

FWIW This may be of some benefit to others.

Clock Tree Synthesis | Physical Design | VLSI Back-End Adventure

Clock Tree Synthesis is a process which makes sure that the clock gets distributed evenly to all sequential elements in a design

www.vlsi-backend-adventure.com

FYI Jitter is just the short-term deviation from ideal position in repetitive time intervals.

Jitter gets amplified by variations in thresholds in a clock tree buffers with added fanout capacitance, and with ps delays by ground capacitance, which is why insertion delays should be minimized.

--- Updated Jan 14, 2024 ---

View attachment 187878

Does this contradict your assumption that CCP has no skew?

Click to expand...

​

Every path has delay but we need to use the term skew for difference of delay.​

This excerpt from your favorite links AMD (you certainly won't get a job there):​

Skew Definition​

Clock skew is the insertion delay difference between the destination clock path and the source clock path: (1) from their common point in the design; (2) to, respectively, the endpoint and startpoint sequential cell clock pins.
In the equation below:

• Tcj is the delay from the common node to the endpoint clock pin.
• Tci is the delay from the common node to the startpoint clock pin:Tskewi,j = Tcj- Tci

Clock Pessimism Removal​

A typical timing path report shows the delay details of both source and destination clock paths, from their root to the sequential cell clock pins. As explained below, the source and destination clocks are analyzed with a different delay, even on their common circuitry.
Common Clock Tree Section

kaz1 said:

Skew Definition

Clock skew is the insertion delay difference between the destination clock path and the source clock path: (1) from their common point in the design; (2) to, respectively, the endpoint and startpoint sequential cell clock pins.
In the equation below:

• Tcj is the delay from the common node to the endpoint clock pin.
• Tci is the delay from the common node to the startpoint clock pin:Tskewi,j = Tcj- Tci

​

Click to expand...

Thankyou for stating the obvious. But the original question is below.

chevuturi said:

do we have skew for common clock path ? if no why ? if yes how do we calculate ?

Click to expand...

The old way was to compute worst case destination delays with clock delays to ensure adequate timing margin.
The modern way is to let Cadence run Clock Tree Synthesis for you to created idealize local or Common Clock Paths with maximum timing margin. (But others like AMD will use their own proprietary tools to do more than Cadence)

If you are pushing the boundaries of speed, you better learn the fundamentals which may include some the parameters I mentioned and refuted by Professor @ThisIsNotSam

kaz1 said:

No, because it is same physical line so it can't have skew with itself.

Click to expand...

A true statement but fallacious in this context.


here are some more obvious characteristics;

1. A differential output clock can have skew with itself when path lengths are not equal
2. It can occur due to variations in signal propagation delays.
3. Clock skew can lead to synchronization issues and data corruption.
4. Skew is measured in picoseconds or nanoseconds, indicating the time difference.
5. High-speed digital systems are more prone to clock skew problems.
6. Skew can be minimized through careful FPGA, ASIC or PCB layout and routing techniques.
7. Advanced clock distribution techniques like delay-locked loops help reduce skew.
8. Skew can impact system performance, causing timing violations and reduced reliability.
9. Proper clock tree design is crucial for minimizing clock skew effects.
10. Accurate characterization of components helps identify potential sources of clock skew. (which includes load capacitance and threshold variance.)
11. In Bi-phase and quadrature clocking schemes asymmetry does have skew with itself measure by the duty cycle error or -dB of the 2f - 1f harmonic on a spectrum analyzer, where a perfect square wave has null even harmonics.

Let's explore the concepts of fanout capacitance and device threshold variance in the context of digital integrated circuit design:

1. Fanout Capacitance:
   • Definition: Fanout capacitance refers to the total capacitance seen by a gate output due to its connection to multiple inputs.
   • Importance: In digital circuits, gates drive other gates, and the capacitive load they drive depends on the number and characteristics of the gates connected to their output. As the number of fanout gates increases, the total capacitance seen by the driving gate increases, leading to increased RC delays and potential performance degradation.
   • Mitigation: Techniques such as buffering, inserting repeaters, or optimizing logic structures can be employed to manage fanout capacitance and minimize its impact on signal propagation delays.
2. Device Threshold Variance:
   • Definition: Device threshold variance refers to variations in the threshold voltage (Vth) of individual transistors within a digital circuit.
   • Importance: Threshold voltage variations can lead to variations in transistor switching characteristics, affecting the speed and reliability of the circuit. This variability can arise due to manufacturing process variations.
   • Mitigation: To address device threshold variance, designers employ techniques like transistor sizing, biasing, and use of process corner models during the design phase. Additionally, the use of advanced fabrication processes and technologies that reduce device parameter variations can help mitigate this issue.

I have a different opinion than @ThisIsNotSam on my previous statement of pF and gate input threshold voltage tolerances ( not for Cadence tools per se, but in general)

In the context of Clock Tree Synthesis (CTS) and overall digital circuit design, both fanout capacitance and device threshold variance are critical factors that impact the performance and reliability of the design.

• CTS and Fanout Capacitance:
  • During CTS, the fanout capacitance is considered in the analysis of signal delays. The clock tree needs to be optimized to manage the effects of fanout capacitance to meet timing requirements. Buffering and repeater insertion may be applied strategically to control signal integrity.
• CTS and Device Threshold Variance:
  • Device threshold variance can contribute to variations in signal arrival times and affect the overall performance of the clock distribution. Techniques to address threshold variations may include careful transistor sizing, biasing, and considering process corners during the optimization of the clock tree.

Although I have never had a need to use the Cadence CTS tools , this is my understanding of what to expect;

Minimizing Routing Resources:
CTS ought to optimize the routing resources used by the clock signals. This involves planning the distribution of the clock signals to different parts of the chip efficiently, minimizing wire lengths, and reducing the overall capacitance.

Minimizing Area Occupied by Clock Repeaters:
Clock repeaters are often used in large IC designs to improve clock signal quality and mitigate clock skew. However, they consume area on the chip. CTS ought to place clock repeaters judiciously to minimize the overall area impact.

Meeting Acceptable Clock Skew:
Clock skew refers to the variation in arrival times of the clock signal at different points in the circuit.
CTS ought to balance and minimize clock skew to ensure synchronous operation of the design.

Reasonable Clock Latency:
Clock latency is the time delay experienced by the clock signal as it propagates through the clock distribution network.
CTS optimizes the clock tree to minimize latency while meeting design requirements.

Clock Transition Time:
This refers to the time taken by the clock signal to transition from one logic level to another.
CTS considers transition times to ensure that the clock signal arrives at different points in the circuit with sufficient time margin for reliable operation.

Minimum Pulse Width and Duty Cycle Requirements:
Sequential elements in digital designs often have requirements on the minimum pulse width and duty cycle of the clock signal for proper functioning.
All requirements must be met for all elements in the design.

Tony S. EE since 1975

Hi Tony. You seem to have very limited knowledge of CPPR, throwing random terms from PCB design and whatever else you could find on VLSI websites about CTS and how STA works in a clock tree. This is *not* what OP is asking, you are muddying the water. On top of that, you have this continuous thing about a job at AMD?! I really don't get it but I will leave at that and put you on my ignore list moving forward. On other topics you seemed to have spewed even higher BS level with AI generated answers that are not exactly what I would call good.

For other forum users, please refer to kaz1 answer. You want deep insights into CPPR, Innovus documentation has a great chapter on it. Also worth reading is the (A)OCV derating behavior as it is intimately linked to CPPR. This is all you need to know.