Sizing of transistors in low voltage to high voltage level shifter

Hi all,

I am trying to design a low voltage to high voltage level shifter circuit. The high voltage control signal should switch between 15 and 18V. I got the design from 'A low voltage to high voltage level shifter circuit for MEMS application' by Pan et. al. I have included a screenshot of the design below.


It would be a great help if anyone can help me with how to size the transistors in the circuit. Thanks in advance.

rissenaj

The driver nfet should be large compared the PFET at the top so it is able to flip the level shifter. This design is mainly done to protect the device from breaking down by reducing the voltage drop across each of the transistors. Each transistors will have a specific VDSmax, VGSmax etc. The bias voltages have to made in such a way that these voltages are not exceeded. All the bias transistos can be the same provided they are able to take care of the relaibility. In case it is not possible to generate the various Vbias, then one goes and plays with the sizes to get the reliability
Bottom line the sizing should meet the relaibility checks and whether the cell is able to flip..

artmalik said:

The driver nfet should be large compared the PFET at the top so it is able to flip the level shifter. This design is mainly done to protect the device from breaking down by reducing the voltage drop across each of the transistors. Each transistors will have a specific VDSmax, VGSmax etc. The bias voltages have to made in such a way that these voltages are not exceeded. All the bias transistos can be the same provided they are able to take care of the relaibility. In case it is not possible to generate the various Vbias, then one goes and plays with the sizes to get the reliability
Bottom line the sizing should meet the relaibility checks and whether the cell is able to flip..

Click to expand...

Thanks...So the NMOS at the bottom should be strong so that it can flip the level shifter. I was wondering if there is some kind of equation which would say that the NMOS should be atleast this wide. It is my understanding that the voltage at the drain side of the PMOS should be atleast |Vtp| smaller that HVCC for the regenerative circuit to work and flip the output and the PMOS at the top will be in linear mode of operation. And the driver NMOS will be in saturation when its input voltage is high. But when I am calculating for the required width of NMOS, I am getting like Wn > 1/6Wp. What am I doing wrong?

In my design the HVCC is 20V, all are 5V CMOS transistors and I am assuming Vtn = |Vtp| = 0.7V. I am having the bias voltages as 5V, 10V and 15V and the o/p should switch between 20V and 15V approx. The circuit has 3 stages of drain connected NMOS and PMOS in between the top PMOS stage and the bottom NMOS drive.

This circuit shows no body terminals and you probably need to
deal with that; 15V Vgb is going to pop any 5V transistor that
doesn't have a high voltage independently bias-able well. I'd
bet this was done on an SOI technology.

The PMOS cross coupled pair has to be made weaker than
the whole stack. You may elect to use resistors for this,
they will have a more consistent current limiting.

Aside from this, sizing plays in prop delay primarily, and
the transition currents (dynamic Idd).

Managing the bias rails so that your level shifter stack
consistently has enough grunt to flip over the PMOS
pair, wants some attention. So does the initialization of
the high side, when the high side rail does not provide
enough headroom for all of those stacked VTs to pull
usable current. Power-up in unknown state is your likely
outcome, otherwise, along with misbehavior during the
supply ramp-up time.

dick_freebird said:

This circuit shows no body terminals and you probably need to
deal with that; 15V Vgb is going to pop any 5V transistor that
doesn't have a high voltage independently bias-able well. I'd
bet this was done on an SOI technology.

The PMOS cross coupled pair has to be made weaker than
the whole stack. You may elect to use resistors for this,
they will have a more consistent current limiting.

Aside from this, sizing plays in prop delay primarily, and
the transition currents (dynamic Idd).

Managing the bias rails so that your level shifter stack
consistently has enough grunt to flip over the PMOS
pair, wants some attention. So does the initialization of
the high side, when the high side rail does not provide
enough headroom for all of those stacked VTs to pull
usable current. Power-up in unknown state is your likely
outcome, otherwise, along with misbehavior during the
supply ramp-up time.

Click to expand...

Hi,

Thank you very much for your reply. I am really sorry for the late response. Yeah, it was done in an SOI process. Mine is not an SOI process. Hence I have tied the source and body of each transistor together to overcome this Vgb issue. I have done spice simulations using the above method and it seems to be working fine. Is there a problem which I have overlooked? Could you please give some more insight into how the power up in uninitialized state can happen?

Thanks
rissenaj