Sizing of PMOS driver of LDO in "CADENCE"

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kishore680

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I am designing LDO with PMOS as pass transistor , It should support current upto 50mA. SO width of PMOS should be very very high. But in cadence maximum width i can give is 100u. i need ratio of 6m/1u W/L. How to do that in cadence?
 

If you need something like say 6mm of Wtotal, name your PMOS instance like NAME<59:0> with the maximum W that the technology permits (100um).
That will give you the 6mm, because you end up in your netlist with 60 PMOS devices of W=100u and L=1u.

I do not Know what technology you are using, but why are you using such a big L?
Lower your L, which makes you need a smaller W/L ratio and therefore a smaller layout.
 
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Thank you i am using UMC180 . If i use L as 180nm even then W should be quite high . BEcause to drive 50mA keeping Vds=0.2. I need very very high W/L.
 

Yes, if you want such a low dropout it will cost you quite big layout area (bigger W/L).
Nevertheless, I think you do not need to have such a high value for L.
So, if you reduce your L value, in order to maintain the same W/L relation (to have the low VDS drop that you want) you lower you W.
This way you achieve less layout area
You just need to check if your leakage is small enough (due to the smaller L) to be discarded when the PowerMOS is open!
 

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