chandu.kurapati
Full Member level 3
- Joined
- Oct 31, 2013
- Messages
- 186
- Helped
- 5
- Reputation
- 10
- Reaction score
- 5
- Trophy points
- 1,298
- Location
- Bengaluru, India
- Activity points
- 2,778
Hi all,
I want to implement the SWD protocol with two GPIO pins one as a SWDIO and another SWCLK, but i have some conflict about the clock frequency.
What is the acceptable clock frequency of the SWD protocol, there is any range of frequency to configure the SWD, I couldn't find it in any document but have to provide some delay between the SWCLK set and reset operations.
I don't understand the how much delay to provide in between the set and reset operations, i think that delay depend on the clock frequency.
can any one help me about the SWD frequency conflict.
Thanks & Regards,
Chandu.Kurapati.
I want to implement the SWD protocol with two GPIO pins one as a SWDIO and another SWCLK, but i have some conflict about the clock frequency.
What is the acceptable clock frequency of the SWD protocol, there is any range of frequency to configure the SWD, I couldn't find it in any document but have to provide some delay between the SWCLK set and reset operations.
I don't understand the how much delay to provide in between the set and reset operations, i think that delay depend on the clock frequency.
can any one help me about the SWD frequency conflict.
Thanks & Regards,
Chandu.Kurapati.